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ORCIDIbrahim Hur
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2020 – today
- 2024
[c27]Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur:
HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures. HPCA 2024: 1012-1028- [i3]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Accurate and Scalable Many-Node Simulation. CoRR abs/2401.09877 (2024) - 2023
- [j16]Sriram Aananthakrishnan
, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche:
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43(5): 78-87 (2023) - [c26]Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur:
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS 2023: 124-133 - 2022
- [c25]Pascal Costanza, Ibrahim Hur, Timothy G. Mattson:
Towards a GraphBLAS Implementation for Go. IPDPS Workshops 2022: 1-4 - [c24]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS 2022: 322-331 - [i2]Stijn Eyerman, Ibrahim Hur:
Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. CoRR abs/2209.13265 (2022) - 2021
- [j15]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. 20(1): 78-81 (2021) - [j14]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. 20(2): 90-93 (2021) - [j13]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. 18(3): 33:1-33:23 (2021) - [c23]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO 2021: 767-778 - 2020
- [j12]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. 19(1): 30-33 (2020) - [c22]Sriram Aananthakrishnan, Robert Pawlowski, Joshua B. Fryman, Ibrahim Hur:
Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture. HPEC 2020: 1-2 - [c21]Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur:
Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC 2020: 1-7 - [c20]Balasubramanian Seshasayee, Joshua B. Fryman, Ibrahim Hur:
Hash Table Scalability on Intel PIUMA. HPEC 2020: 1-2 - [i1]Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz:
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR abs/2010.06277 (2020)
2010 – 2019
- 2018
- [j11]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. 17(1): 55-58 (2018) - [c19]Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur:
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT 2018: 28:1-28:11 - [c18]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS 2018: 179-188 - [c17]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur:
Many-core graph workload analysis. SC 2018: 22:1-22:11 - 2017
- [c16]Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis:
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. HPEC 2017: 1-7 - 2015
- [j10]A. Vapirev, Jan Deca, Giovanni Lapenta, Stefano Markidis, Ibrahim Hur, Jean-Luc Cambier:
Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code. Concurr. Comput. Pract. Exp. 27(3): 581-593 (2015) - 2014
- [j9]Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout:
An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. 11(3): 28:1-28:25 (2014) - [c15]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Undersubscribed threading on clustered cache architectures. HPCA 2014: 678-689 - [c14]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. ROSS@ICS 2014: 7:1-7:7 - 2012
- [j8]Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Profiling and Optimizing Transactional Memory Applications. Int. J. Parallel Program. 40(1): 25-56 (2012) - [j7]Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. Integr. 45(3): 237-245 (2012) - [j6]Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Resource-bounded multicore emulation using Beefarm. Microprocess. Microsystems 36(8): 620-631 (2012) - [j5]J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8(4): 31:1-31:20 (2012) - [c13]Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout:
Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT 2012: 3-12 - 2011
- [j4]Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). SIGMETRICS Perform. Evaluation Rev. 39(3): 19 (2011) - [c12]Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory. PACT 2011: 199-200 - [c11]Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems. PACT 2011: 221-231 - [c10]Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371 - [c9]Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. ARC 2011: 350-362 - [c8]Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. FCCM 2011: 146-153 - [c7]Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330 - [c6]Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
RMS-TM: a comprehensive benchmark suite for transactional memory systems. ICPE 2011: 335-346 - 2010
- [j3]Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Rivière, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel:
The Velox Transactional Memory Stack. IEEE Micro 30(5): 76-87 (2010) - [c5]Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Discovering and understanding performance bottlenecks in transactional applications. PACT 2010: 285-294
2000 – 2009
- 2009
- [c4]Ibrahim Hur, Calvin Lin:
Feedback mechanisms for improving probabilistic memory prefetching. HPCA 2009: 443-454 - 2008
- [c3]Ibrahim Hur, Calvin Lin:
A comprehensive approach to DRAM power management. HPCA 2008: 305-316 - 2007
- [j2]Ibrahim Hur, Calvin Lin:
Memory scheduling for modern microprocessors. ACM Trans. Comput. Syst. 25(4): 10 (2007) - 2006
- [j1]Ibrahim Hur, Calvin Lin:
Adaptive History-Based Memory Schedulers for Modern Processors. IEEE Micro 26(1): 22-29 (2006) - [c2]Ibrahim Hur, Calvin Lin:
Memory Prefetching Using Adaptive Stream Detection. MICRO 2006: 397-408 - 2004
- [c1]Ibrahim Hur, Calvin Lin:
Adaptive History-Based Memory Schedulers. MICRO 2004: 343-354
Coauthor Index
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last updated on 2024-08-21 20:28 CEST by the dblp team
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