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ORCIDGautam R. Gangasani
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2020 – today
- 2024
[c5]Gautam R. Gangasani, A. Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. B. Ramakrishna, U. K. Shukla:
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. VLSI Technology and Circuits 2024: 1-2- 2022
- [c4]Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. B. Ramakrishna, S. Shi, S. Parker, U. K. Shukla, W. Kelly, W. Su, Z. Yu:
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. ISSCC 2022: 122-124
2010 – 2019
- 2019
- [j5]Gautam R. Gangasani
, Peter R. Kinget:
A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 803-807 (2019) - 2018
- [c3]Gautam R. Gangasani, Peter R. Kinget:
A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS. ESSCIRC 2018: 182-185 - 2014
- [j4]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli:
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 49(11): 2474-2489 (2014) - 2012
- [j3]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli:
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(8): 1828-1841 (2012) - 2011
- [c2]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli:
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology. CICC 2011: 1-4
2000 – 2009
- 2008
- [j2]G. Reddy Gangasani, Peter R. Kinget:
Time-Domain Model for Injection Locking in Nonharmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1648-1658 (2008) - 2006
- [j1]G. Reddy Gangasani, Peter R. Kinget:
A Time-Domain Model for Predicting the Injection Locking Bandwidth of Nonharmonic Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1035-1038 (2006) - [c1]G. Reddy Gangasani, Peter R. Kinget:
Injection-lock dynamics in non-harmonic oscillators. ISCAS 2006
Coauthor Index
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