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ORCIDAlberto Ros 0001
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- affiliation: University of Murcia, Computer Engineering Department, Spain
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2020 – today
- 2024
[j38]Víctor Nicolás-Conesa
, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems 104: 104975 (2024)- [j37]Alberto Ros, Alexandra Jimborean:
Wrong-Path-Aware Entangling Instruction Prefetcher. IEEE Trans. Computers 73(2): 548-559 (2024) - [c73]Sebastian S. Kim, Alberto Ros:
Effective Context-Sensitive Memory Dependence Prediction. HPCA 2024: 515-527 - [c72]Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros:
Alternate Path μ-op Cache Prefetching. ISCA 2024: 1230-1245 - [c71]Sumon Nath, Agustín Navarro-Torres, Alberto Ros, Biswabandan Panda:
Secure Prefetching for Secure Cache Systems. MICRO 2024: 92-104 - [c70]Juan M. Cebrian, Magnus Jahre, Alberto Ros:
Temporarily Unauthorized Stores: Write First, Ask for Permission Later. MICRO 2024: 810-822 - [c69]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Alberto Ros:
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO 2024: 840-855 - [c68]Per Ekemark, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras:
A First Exploration of Fine-Grain Coherence for Integrity Metadata. SEED 2024: 62-72 - [i3]Milan Pandurov, Lukas Humbel, Dmitry Sepp, Adamos Ttofari, Leon Thomm, Do Le Quoc, Siddharth Chandrasekaran, Sharan Santhanam, Chuan Ye, Shai Bergman, Wei Wang, Sven Lundgren, Konstantinos Sagonas, Alberto Ros:
Flexible Swapping for the Cloud. CoRR abs/2409.13327 (2024) - 2023
- [j36]Bhargavi R. Upadhyay, Alberto Ros, Supriya M.:
Fine-grain data classification to filter token coherence traffic. J. Parallel Distributed Comput. 171: 40-53 (2023) - [j35]Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras:
Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. 173: 94-106 (2023) - [c67]Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros:
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT 2023: 1-13 - [c66]Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros:
Rebasing Microarchitectural Research with Industry Traces. IISWC 2023: 100-114 - [c65]Emilio Domínguez-Sánchez, Alberto Ros:
MBPlib: Modular Branch Prediction Library. ISPASS 2023: 71-80 - 2022
- [j34]Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean:
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78(1): 919-944 (2022) - [j33]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33(1): 1-13 (2022) - [j32]Juan M. Cebrian, Thibaud Balem, Adrián Barredo, Marc Casas, Miquel Moretó, Alberto Ros, Alexandra Jimborean:
Compiler-Assisted Compaction/Restoration of SIMD Instructions. IEEE Trans. Parallel Distributed Syst. 33(4): 779-791 (2022) - [c64]Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz:
Composite Instruction Prefetching. ICCD 2022: 471-478 - [c63]Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros:
Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. IISWC 2022: 51-64 - [c62]Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros:
Free atomics: hardware atomic operations without fences. ISCA 2022: 14-26 - [c61]Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros:
Exploring Instruction Fusion Opportunities in General Purpose Processors. MICRO 2022: 199-212 - [c60]Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros:
Berti: an Accurate Local-Delta Data Prefetcher. MICRO 2022: 975-991 - [c59]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP 2022: 157-164 - 2021
- [j31]Bhargavi R. Upadhyay, Alberto Ros, Jalpa Shah:
Efficient classification of private memory blocks. J. Parallel Distributed Comput. 157: 256-268 (2021) - [c58]Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras:
TSOPER: Efficient Coherence-Based Strict Persistency. HPCA 2021: 125-138 - [c57]Alberto Ros, Alexandra Jimborean:
A Cost-Effective Entangling Prefetcher for Instructions. ISCA 2021: 99-111 - [c56]Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros:
Splash-4: Improving Scalability with Lock-Free Constructs. ISPASS 2021: 235-236 - [c55]Eduardo José Gómez-Hernández, Juan M. Cebrian, J. Rubén Titos Gil, Stefanos Kaxiras, Alberto Ros:
Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. MICRO 2021: 337-349 - [c54]Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras:
ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO 2021: 1296-1308 - [c53]Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu:
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. SEED 2021: 89-100 - [i2]Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu:
On Value Recomputation to Accelerate Invisible Speculation. CoRR abs/2102.10932 (2021) - 2020
- [j30]Alberto Ros, Alexandra Jimborean:
The Entangling Instruction Prefetcher. IEEE Comput. Archit. Lett. 19(2): 84-87 (2020) - [j29]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145: 111-123 (2020) - [j28]Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander:
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE Trans. Computers 69(11): 1584-1595 (2020) - [j27]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31(6): 1301-1315 (2020) - [c52]Sawan Singh, Alexandra Jimborean, Alberto Ros:
Regional Out-of-Order Writes in Total Store Order. PACT 2020: 205-216 - [c51]Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean:
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. PACT 2020: 241-254 - [c50]Alberto Ros, Stefanos Kaxiras:
Speculative Enforcement of Store Atomicity. MICRO 2020: 555-567 - [c49]Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros:
Boosting Store Buffer Efficiency with Store-Prefetch Bursts. MICRO 2020: 568-580 - [c48]Bhargavi R. Upadhyay, Alberto Ros, Murty NS:
TLB-based Block-Grain Classification of Private Data. PDP 2020: 122-130
2010 – 2019
- 2019
- [j26]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio:
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30(11): 2608-2623 (2019) - [c47]Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander:
Ghost loads: what is the cost of invisible speculation? CF 2019: 153-163 - [c46]Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras:
Filter caching for free: the untapped potential of the store-buffer. ISCA 2019: 436-448 - [c45]Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander:
Efficient invisible speculative execution through selective delay and value prediction. ISCA 2019: 723-735 - 2018
- [j25]José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio:
Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. 113: 179-194 (2018) - [j24]Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu:
Mending Fences with Self-Invalidation and Self-Downgrade. Log. Methods Comput. Sci. 14(1) (2018) - [j23]Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros:
Non-Speculative Load Reordering in Total Store Ordering. IEEE Micro 38(3): 48-57 (2018) - [j22]Alexandra Jimborean, Per Ekemark, Jonatan Waern, Stefanos Kaxiras, Alberto Ros:
Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation. IEEE Trans. Parallel Distributed Syst. 29(3): 527-541 (2018) - [j21]Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez:
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction. IEEE Trans. Parallel Distributed Syst. 29(5): 1188-1201 (2018) - [c44]Alberto Ros, Stefanos Kaxiras:
Non-Speculative Store Coalescing in Total Store Order. ISCA 2018: 221-234 - [c43]Alberto Ros, Stefanos Kaxiras:
The Superfluous Load Queue. MICRO 2018: 95-107 - 2017
- [j20]Juan M. Cebrian, Ricardo Fernández Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros:
A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. 29(2) (2017) - [j19]Joan J. Valls, Alberto Ros, María Engracia Gómez, Julio Sahuquillo:
The Tag Filter Architecture: An energy-efficient cache and directory design. J. Parallel Distributed Comput. 100: 193-202 (2017) - [j18]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. 73(10): 4428-4443 (2017) - [j17]Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato:
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. IEEE Trans. Parallel Distributed Syst. 28(8): 2401-2413 (2017) - [j16]Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras:
Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. IEEE Trans. Parallel Distributed Syst. 28(12): 3413-3425 (2017) - [c42]Alexandra Jimborean, Jonatan Waern, Per Ekemark, Stefanos Kaxiras, Alberto Ros:
Automatic detection of extended data-race-free regions. CGO 2017: 14-26 - [c41]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS 2017: 20:1-20:10 - [c40]Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras:
Non-Speculative Load-Load Reordering in TSO. ISCA 2017: 187-200 - 2016
- [j15]Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras:
Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. ACM Trans. Archit. Code Optim. 13(1): 1:1-1:22 (2016) - [j14]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. 72(2): 612-638 (2016) - [j13]Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato:
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 27(3): 748-761 (2016) - [j12]Alberto Ros, Alexandra Jimborean:
A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence. IEEE Trans. Parallel Distributed Syst. 27(11): 3101-3115 (2016) - [c39]Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras:
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. PACT 2016: 433-434 - [c38]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS 2016: 100-112 - [c37]Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu:
Fencing Programs with Self-Invalidation and Self-Downgrade. FORTE 2016: 19-35 - [c36]Joan J. Valls, María Engracia Gómez, Alberto Ros, Julio Sahuquillo:
A Directory Cache with Dynamic Private-Shared Partitioning. HiPC 2016: 382-391 - [c35]Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez, José Duato:
TokenTLB: A Token-Based Page Classification Approach. ICS 2016: 26:1-26:13 - [c34]Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, Alberto Ros:
Splash-3: A properly synchronized benchmark suite for contemporary research. ISPASS 2016: 101-111 - [c33]Alberto Ros, Stefanos Kaxiras:
Racer: TSO consistency via race detection. MICRO 2016: 33:1-33:13 - [i1]Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu:
Mending Fences with Self-Invalidation and Self-Downgrade. CoRR abs/1611.07372 (2016) - 2015
- [j11]Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras:
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. ACM Trans. Archit. Code Optim. 12(3): 26:1-26:21 (2015) - [j10]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers 64(6): 1534-1547 (2015) - [j9]Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez:
PS-Cache: an energy-efficient cache design for chip multiprocessors. J. Supercomput. 71(1): 67-86 (2015) - [j8]Alberto Ros, Manuel E. Acacio:
DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. 71(3): 781-807 (2015) - [j7]Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez:
PS directory: a scalable multilevel directory cache for CMPs. J. Supercomput. 71(8): 2847-2876 (2015) - [c32]Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras:
An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. PACT 2015: 317-330 - [c31]Juan M. Cebrian, Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Early Experiences with Separate Caches for Private and Shared Data. e-Science 2015: 572-579 - [c30]Alberto Ros, Stefanos Kaxiras:
Fast&Furious: A Tool for Detecting Covert Racing. PARMA-DITAM@HiPEAC 2015: 1-6 - [c29]Alberto Ros, Mahdad Davari, Stefanos Kaxiras:
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. HPCA 2015: 186-197 - [c28]Stefanos Kaxiras, David Klaftenegger, Magnus Norgren, Alberto Ros, Konstantinos Sagonas:
Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory. HPDC 2015: 3-14 - [c27]Alberto Ros, Alexandra Jimborean:
A Dual-Consistency Cache Coherence Protocol. IPDPS 2015: 1119-1128 - [c26]Alberto Ros, Stefanos Kaxiras:
Callback: efficient synchronization without invalidation with a directory just for spin-waiting. ISCA 2015: 427-438 - [c25]Joan J. Valls, Julio Sahuquillo, Alberto Ros, María Engracia Gómez:
The Tag Filter Cache: An Energy-Efficient Approach. PDP 2015: 182-189 - 2014
- [c24]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) 2014: 254-265 - 2013
- [j6]Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato:
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks. IEEE Trans. Computers 62(3): 482-495 (2013) - [c23]Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez:
PS-cache: An energy-efficient cache design for chip multiprocessors. PACT 2013: 407 - [c22]José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio:
Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS 2013: 2545-2548 - [c21]Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato:
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors. ICPP 2013: 562-571 - [c20]Stefanos Kaxiras, Alberto Ros:
A new perspective for efficient virtual-cache coherence. ISCA 2013: 535-546 - [c19]José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio:
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS 2013: 237-244 - 2012
- [j5]Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García:
DAPSCO: Distance-aware partially shared cache organization. ACM Trans. Archit. Code Optim. 8(4): 25:1-25:19 (2012) - [j4]Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61(5): 593-606 (2012) - [c18]Alberto Ros, Stefanos Kaxiras:
Complexity-effective multicore coherence. PACT 2012: 241-252 - [c17]Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez, José Duato:
PS-Dir: a scalable two-level directory cache. PACT 2012: 451-452 - [c16]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED 2012: 51-56 - [c15]Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato:
Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems. ISPA 2012: 691-696 - [c14]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD 2012: 43-50 - [c13]Stefanos Kaxiras, Alberto Ros:
Efficient, snoopless, System-on-Chip coherence. SoCC 2012: 230-235 - 2011
- [c12]Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García:
Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation. ICPP 2011: 51-62 - [c11]Francisco Triviño, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez, Alberto Ros:
Self-related traces: An alternative to full-system simulation for NoCs. HPCS 2011: 819-824 - [c10]Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato:
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks. ISCA 2011: 93-104 - 2010
- [j3]Alberto Ros, Manuel E. Acacio, José M. García:
A scalable organization for distributed directories. J. Syst. Archit. 56(2-3): 77-87 (2010) - [j2]Alberto Ros, Manuel E. Acacio, José M. García:
A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 21(12): 1779-1792 (2010) - [c9]Alberto Ros, Manuel E. Acacio:
Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops 2010: 87-97 - [c8]Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
EMC2: Extending Magny-Cours coherence for large-scale servers. HiPC 2010: 1-10
2000 – 2009
- 2009
- [c7]Alberto Ros, Manuel E. Acacio, José M. García:
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT 2009: 11-27 - [c6]Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García:
Distance-aware round-robin mapping for large NUCA caches. HiPC 2009: 79-88 - 2008
- [j1]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García:
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68(11): 1413-1424 (2008) - [c5]Alberto Ros, Manuel E. Acacio, José M. García:
Scalable Directory Organization for Tiled CMP Architectures. CDES 2008: 112-118 - [c4]Alberto Ros, Manuel E. Acacio, José M. García:
DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS 2008: 1-11 - 2007
- [c3]Alberto Ros, Manuel E. Acacio, José M. García:
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC 2007: 147-160 - 2006
- [c2]Alberto Ros, Manuel E. Acacio, José M. García:
An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers 2006: 321-330 - 2005
- [c1]Alberto Ros, Manuel E. Acacio, José M. García:
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par 2005: 582-591
Coauthor Index