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2020 – today
- 2021
[j30]Cristobal Ortega, Lluc Alvarez, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose, Miquel Moretó:
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption. IEEE Trans. Computers 70(1): 1-16 (2021)- 2020
- [j29]Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero:
Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Future Gener. Comput. Syst. 112: 832-847 (2020) - [j28]Adrián Barredo
, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó:
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. J. Supercomput. 76(3): 1960-1979 (2020) - [j27]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3): 2039-2062 (2020) - [c60]Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco A. Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas, Luis Villa:
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS 2020: 1-6 - [c59]Abbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó:
A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. FPL 2020: 57-64 - [c58]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. HPCA 2020: 717-728 - [c57]Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero:
RICH: implementing reductions in the cache hierarchy. ICS 2020: 16:1-16:13 - [c56]Isaac Sánchez Barrera, David Black-Schaffer, Marc Casas, Miquel Moretó, Anastasiia Stupnikova, Mihail Popov:
Modeling and optimizing NUMA effects and prefetching with machine learning. ICS 2020: 34:1-34:13 - [c55]Ivan Perez, Enrique Vallejo, Miquel Moretó, Ramón Beivide:
BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass. ISPASS 2020: 47-57
2010 – 2019
- 2019
- [j26]Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero:
The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. 1(1): 3-13 (2019) - [j25]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero:
On the maturity of parallel applications for asymmetric multi-core processors. J. Parallel Distributed Comput. 127: 105-115 (2019) - [j24]Thomas Grass, Trevor E. Carlson, Alejandro Rico, Germán Ceballos, Eduard Ayguadé, Marc Casas, Miquel Moretó:
Sampled Simulation of Task-Based Programs. IEEE Trans. Computers 68(2): 255-269 (2019) - [j23]Adrià Armejach, Marc Casas, Miquel Moretó:
Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. 75(9): 5717-5740 (2019) - [c54]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
POSTER: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480 - [c53]Adrián Barredo, Jonathan C. Beard, Miquel Moretó:
POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns. PACT 2019: 483-484 - [c52]Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas:
Power efficient job scheduling by predicting the impact of processor manufacturing variability. ICS 2019: 296-307 - [c51]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs. ICS 2019: 380-391 - [c50]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
A Vulnerability Factor for ECC-protected Memory. IOLTS 2019: 176-181 - [c49]Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas:
Design Space Exploration of Next-Generation HPC Machines. IPDPS 2019: 54-65 - [c48]Neiel I. Leyva-Santes, Ivan Perez, César-Alejandro Hernández-Calderón, Enrique Vallejo, Miquel Moretó, Ramón Beivide, Marco Antonio Ramírez Salinas, Luis A. Villa-Vargas:
Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. ISUM 2019: 237-248 - [c47]Alejandro Rico, Isaac Sánchez Barrera, José A. Joao, Joshua Randall, Marc Casas, Miquel Moretó:
On the Benefits of Tasking with OpenMP. IWOMP 2019: 217-230 - [c46]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs: poster. PPoPP 2019: 415-416 - 2018
- [j22]Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero:
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. J. Supercomput. 74(6): 2627-2637 (2018) - [j21]Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas:
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Trans. Parallel Distributed Syst. 29(5): 1174-1187 (2018) - [j20]Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. IEEE Trans. Parallel Distributed Syst. 29(9): 1961-1974 (2018) - [c45]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Stencil codes on a vector length agnostic architecture. PACT 2018: 13:1-13:12 - [c44]Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero:
Architectural Support for Task Dependence Management with Flexible Software Scheduling. HPCA 2018: 283-295 - [c43]Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. ICS 2018: 207-217 - [c42]Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó:
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. ICS 2018: 218-228 - [c41]Cristobal Ortega, Victor Garcia, Miquel Moretó, Marc Casas, Roxana Rusitoru:
Data Prefetching on In-order Processors. HPCS 2018: 322-329 - [c40]Calvin Bulla, Lluc Alvarez, Miquel Moretó, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose:
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks. IISWC 2018: 80-81 - [c39]Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Graph partitioning applied to DAG scheduling to reduce NUMA effects. PPOPP 2018: 419-420 - [c38]Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas:
Runtime-assisted cache coherence deactivation in task parallel programs. SC 2018: 35:1-35:12 - [c37]Kallia Chronaki, Marc Casas, Miquel Moretó, Jaume Bosch, Rosa M. Badia:
TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism. ISC 2018: 389-409 - [i2]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
Memory Vulnerability: A Case for Delaying Error Reporting. CoRR abs/1810.06472 (2018) - 2017
- [j19]Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Scheduling Techniques for Asymmetric Multi-Core Systems. IEEE Trans. Parallel Distributed Syst. 28(7): 2074-2087 (2017) - [c36]Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. Euro-Par 2017: 247-259 - [c35]Ilia Pietri, Sicong Zhuang, Marc Casas, Miquel Moretó, Rizos Sakellariou:
Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor. Euro-Par Workshops 2017: 439-451 - [c34]Cristobal Ortega, Miquel Moretó, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose:
libPRISM: an intelligent adaptation of prefetch and SMT levels. ICS 2017: 28:1-28:10 - [c33]Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi:
ATM: Approximate Task Memoization in the Runtime System. IPDPS 2017: 1140-1150 - [c32]Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky:
iQ: An Efficient and Flexible Queue-Based Simulation Framework. MASCOTS 2017: 143-149 - [c31]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. SBAC-PAD 2017: 73-80 - 2016
- [j18]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. ACM Trans. Archit. Code Optim. 12(4): 41:1-41:22 (2016) - [j17]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero:
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12(4): 60:1-60:26 (2016) - [j16]Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. IEEE Trans. Computers 65(1): 256-269 (2016) - [j15]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 22(1): 16:1-16:26 (2016) - [c30]Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. PACT 2016: 275-286 - [c29]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. PACT 2016: 415-417 - [c28]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. ICS 2016: 5:1-5:12 - [c27]Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
CATA: Criticality Aware Task Acceleration for Multicore Processors. IPDPS 2016: 413-422 - [c26]Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Eduard Ayguadé:
TaskPoint: Sampled simulation of task-based programs. ISPASS 2016: 296-306 - [c25]Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó:
MUSA: a multi-level simulation approach for next-generation HPC machines. SC 2016: 526-537 - 2015
- [c24]Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. PACT 2015: 379-391 - [c23]Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Aware Architectures. Euro-Par 2015: 16-27 - [c22]Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero:
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. ISCA 2015: 720-732 - [c21]Raul Vidal, Marc Casas, Miquel Moretó, Dimitrios Chasapis, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. IWOMP 2015: 60-72 - [c20]Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. SC 2015: 53:1-53:12 - [i1]David Prat, Cristobal Ortega, Marc Casas, Miquel Moretó, Mateo Valero:
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7. CoRR abs/1501.02282 (2015) - 2014
- [j14]Qixiao Liu, Víctor Jiménez, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Per-task Energy Accounting in Computing Systems. IEEE Comput. Archit. Lett. 13(2): 85-88 (2014) - [j13]Mateo Valero, Miquel Moretó, Marc Casas, Eduard Ayguadé, Jesús Labarta:
Runtime-Aware Architectures: A First Approach. Supercomput. Front. Innov. 1(1): 29-44 (2014) - [c19]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014: 111-123 - [c18]Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Alex Ramírez:
Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors. Euro-Par Workshops (2) 2014: 218-229 - 2013
- [j12]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Fair CPU time accounting in CMP+SMT processors. ACM Trans. Archit. Code Optim. 9(4): 50:1-50:25 (2013) - [j11]Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hardware support for accurate per-task energy metering in multicore systems. ACM Trans. Archit. Code Optim. 10(4): 34:1-34:27 (2013) - [c17]Juan A. Colmenares, Gage Eads, Steven A. Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanovic, John Kubiatowicz:
Tessellation: refactoring the OS around explicit resource containers with continuous adaptation. DAC 2013: 76:1-76:10 - [c16]Sylvain Girbal, Miquel Moretó, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia:
On the convergence of mainstream and mission-critical markets. DAC 2013: 185:1-185:10 - [c15]Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic:
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. ISCA 2013: 308-319 - [c14]Cristobal Camarero, Enrique Vallejo, Carmen Martínez, Miquel Moretó, Ramón Beivide:
Task mapping in rectangular twisted tori. SpringSim (HPC) 2013: 15 - 2012
- [j10]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting for Multicore Processors. IEEE Trans. Computers 61(2): 251-264 (2012) - [c13]Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Optimal task assignment in multithreaded processors: a statistical approach. ASPLOS 2012: 235-248 - [c12]Stelios Manousopoulos, Miquel Moretó, Roberto Gioiosa, Nectarios Koziris, Francisco J. Cazorla:
Characterizing thread placement in the IBM POWER7 processor. IISWC 2012: 120-130 - [c11]Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla:
Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. MICRO 2012: 401-412 - 2011
- [j9]Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero:
Simulating Whole Supercomputer Applications. IEEE Micro 31(3): 32-45 (2011) - [j8]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. Trans. High Perform. Embed. Archit. Compil. 3: 3-23 (2011) - 2010
- [j7]José M. Cámara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas:
Twisted Torus Topologies for Enhanced Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 21(12): 1765-1778 (2010) - [c10]Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero:
Load balancing using dynamic cache allocation. Conf. Computing Frontiers 2010: 153-164 - [c9]Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Adapting cache partitioning algorithms to pseudo-LRU replacement policies. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [j6]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting in CMP Processors. IEEE Comput. Archit. Lett. 8(1): 17-20 (2009) - [j5]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Oper. Syst. Rev. 43(2): 86-96 (2009) - [c8]Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. PACT 2009: 203-213 - 2008
- [j4]Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith:
Multicore Resource Management. IEEE Micro 28(3): 6-16 (2008) - [j3]Carmen Martínez, Ramón Beivide, Esteban Stafford, Miquel Moretó, Ernst M. Gabidulin:
Modeling Toroidal Networks with the Gaussian Integers. IEEE Trans. Computers 57(8): 1046-1056 (2008) - [c7]Pedro Ángel Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Sally A. McKee:
Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation 2008: 1941-1948 - [c6]Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luis Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee:
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. EvoWorkshops 2008: 175-183 - [c5]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352 - 2007
- [j2]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups. IEEE Comput. Archit. Lett. 6(1): 1-4 (2007) - [c4]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418 - [c3]José M. Cámara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas:
Mixed-radix Twisted Torus Interconnection Networks. IPDPS 2007: 1-10 - [c2]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177 - 2006
- [j1]Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó:
Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors. Int. J. Parallel Program. 34(3): 193-211 (2006) - [c1]Carmen Martínez, Miquel Moretó, Ramón Beivide, Ernst M. Gabidulin:
A Generalization of Perfect Lee Codes over Gaussian Integers. ISIT 2006: 1070-1074
Coauthor Index
[j30] [j29] [j28] [j27] [c58] [c57] [c56] [j25] [j24] [j23] [c54] [c52] [c51] [c50] [c49] [c47] [c46] [j22] [j21] [j20] [c45] [c44] [c43] [c42] [c41] [c39] [c38] [c37] [i2] [j19] [c36] [c35] [c34] [c33] [c32] [j18] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [i1] [j13] [c18] [j9]
[j29] [j28] [j27] [c60] [c58] [c57] [j26] [j25] [c54] [c52] [c51] [c50] [c46] [j22] [j21] [j20] [c45] [c44] [c43] [c42] [c39] [c38] [i2] [j19] [c36] [c33] [c32] [c31] [j18] [j17] [j16] [j15] [c30] [c29] [c28] [c27] [c25] [c24] [c23] [c22] [c21] [c20] [i1] [j14] [j13] [c19] [j12] [j11] [j10] [c13] [j9] [j8] [c10] [c9] [j6] [j5] [c8] [j4] [c7] [c6] [c5] [j2] [c4] [c2]
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