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2020 – today
- 2022
[j10]Y. Jiang, Sheng Zheng, Z. Jiang, S. Zeng, Zhi-Wei Chen, Xiangyun Zeng, Xiao-YuLuo, Yao Huang:
A connectivity-based method for detecting clumpy structures in molecular clouds. Astron. Comput. 40: 100613 (2022)
2010 – 2019
- 2019
- [j9]Cheng-Chi Lee
, Chun-Ta Li, Zhi-Wei Chen, Shun-Der Chen, Yan-Ming Lai:
A novel authentication scheme for anonymity and digital rights management based on elliptic curve cryptography. Int. J. Electron. Secur. Digit. Forensics 11(1): 96-117 (2019) - 2018
- [j8]Cheng-Chi Lee, Chun-Ta Li, Zhi-Wei Chen, Yan-Ming Lai, Jiann-Cherng Shieh:
An improved E-DRM scheme for mobile environments. J. Inf. Secur. Appl. 39: 19-30 (2018) - [j7]Cheng-Chi Lee, Chun-Ta Li, Zhi-Wei Chen, Yan-Ming Lai:
A Biometric-Based Authentication and Anonymity Scheme for Digital Rights Management System. Inf. Technol. Control. 47(2): 262-274 (2018) - 2014
- [c52]Yen-Chun Hsu, Yu-Sung Wu, Tsung-Han Tsai, Yi Pin Chiu, Chih-Hung Lin, Zhi-Wei Chen:
MicroApp: Architecting Web Application for Non-uniform Trustworthiness in Cloud Computing Environment. SERE (Companion) 2014: 97-106 - 2013
- [j6]Zhi-Wei Chen, Xiao-Ming Wang:
Probabilistic Fatigue Assessment Based on Bayesian Learning for Wind-Excited Long-Span Bridges Installed with WASHMS. Int. J. Distributed Sens. Networks 9 (2013) - [j5]Zhi-Wei Chen, Jin-Tai Yan:
Routability-constrained multi-bit flip-flop construction for clock power reduction. Integr. 46(3): 290-300 (2013) - [j4]Cheng-Chin Chiang, Zhi-Wei Chen, Chen-Ning Yang:
Video-Driven Creation of Virtual Avatars by Component-based Transferring of Facial Expressions. J. Inf. Sci. Eng. 29(6): 1265-1283 (2013) - [c51]Jin-Tai Yan, Zhi-Wei Chen:
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ACM Great Lakes Symposium on VLSI 2013: 203-208 - [c50]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained replacement using spare cells for design changes. ACM Great Lakes Symposium on VLSI 2013: 347-348 - [c49]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout redundant wire insertion for fixing min-delay violations. ISCAS 2013: 1720-1723 - [p2]Mei-Hui Wang, Chang-Shing Lee, Zhi-Wei Chen, Hani Hagras, Su-E Kuo, Hui-Ching Kuo, Hui-Hua Cheng:
A Type-2 FML-Based Fuzzy Ontology for Dietary Assessment. On the Power of Fuzzy Markup Language 2013: 149-168 - [p1]Chang-Shing Lee, Mei-Hui Wang, Chin-Yuan Hsu, Zhi-Wei Chen:
Type-2 Fuzzy Set and Fuzzy Ontology for Diet Application. Advances in Type-2 Fuzzy Sets and Systems 2013: 237-256 - 2012
- [j3]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. Integr. 45(3): 341-347 (2012) - [c48]Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen:
Top-down-based symmetrical buffered clock routing. ACM Great Lakes Symposium on VLSI 2012: 75-78 - [c47]Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen:
Density-reduction-oriented layer assignment for rectangle escape routing. ACM Great Lakes Symposium on VLSI 2012: 275-278 - [c46]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout OPE-predicted redundant wire insertion for clock skew minimization. ICCD 2012: 504-505 - [c45]Zhi-Wei Chen, Jin-Tai Yan:
Utilization of multi-bit flip-flops for clock power reduction. ICECS 2012: 677-680 - [c44]Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen:
Efficient assignment of inter-die signals for die-stacking SiP design. ISCAS 2012: 3254-3257 - [c43]Jin-Tai Yan, Zhi-Wei Chen:
Direction-constrained layer assignment for rectangle escape routing. SoCC 2012: 254-259 - 2011
- [c42]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. DATE 2011: 449-454 - [c41]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained I/O buffer placement for flip-chip designs. DATE 2011: 619-624 - [c40]Chang-Shing Lee, Mei-Hui Wang, Zhi-Wei Chen, Chin-Yuan Hsu, Su-E Kuo, Hui-Ching Kuo, Hui-Hua Cheng, Akio Naito:
Genetic fuzzy markup language for diet application. FUZZ-IEEE 2011: 1791-1798 - [c39]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. ACM Great Lakes Symposium on VLSI 2011: 205-210 - [c38]Jin-Tai Yan, Zhi-Wei Chen:
Pre-assignment RDL routing via extraction of maximal net sequence. ICCD 2011: 65-70 - [c37]Te-En Wei, Zhi-Wei Chen, Chin-Wei Tien, Jain-Shing Wu, Hahn-Ming Lee, Albert B. Jeng:
RePEF - A system for Restoring Packed Executable File for malware analysis. ICMLC 2011: 519-527 - [c36]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware length-matching bus routing. ISPD 2011: 61-68 - [c35]Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen:
Simultaneous escape routing based on routability-driven net ordering. SoCC 2011: 81-86 - 2010
- [j2]Zhi-Wei Chen, Cheng-Chin Chiang, Zi-Tian Hsieh:
Extending 3D Lucas-Kanade tracking with adaptive templates for head pose estimation. Mach. Vis. Appl. 21(6): 889-903 (2010) - [c34]Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen:
Routability-driven partitioning-based IO assignment for flip-chip designs. APCCAS 2010: 1075-1078 - [c33]Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen:
Obstacle-aware longest path using rectangular pattern detouring in routing grids. ASP-DAC 2010: 287-292 - [c32]Jin-Tai Yan, Zhi-Wei Chen:
Two-sided single-detour untangling for bus routing. DAC 2010: 206-211 - [c31]Mei-Hui Wang, Chang-Shing Lee, Zhi-Wei Chen, Chi-Fang Lo, Su-E Kuo, Hui-Ching Kuo, Hui-Hua Cheng:
Property and application of fuzzy ontology for dietary assessment. FUZZ-IEEE 2010: 1-8 - [c30]Jin-Tai Yan, Zhi-Wei Chen:
Resource-constrained timing-driven link insertion for critical delay reduction. ACM Great Lakes Symposium on VLSI 2010: 119-122 - [c29]Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen:
Ordered escape routing via routability-driven pin assignment. ACM Great Lakes Symposium on VLSI 2010: 417-422 - [c28]Zhi-Wei Chen, Jin-Tai Yan:
Routability-driven flip-flop merging process for clock power reduction. ICCD 2010: 203-208 - [c27]Ming-Hui Chu, Yi-Wei Chen, Yuan Kang, Zhi-Wei Chen:
The research of sampling frequency for A DC servo motor speed control system based on neural networks. ICNC 2010: 1401-1405 - [c26]Jin-Tai Yan, Zhi-Wei Chen:
Low-cost low-power bypassing-based multiplier design. ISCAS 2010: 2338-2341 - [c25]Zhi-Wei Chen, Jin-Tai Yan:
Width-constrained wire sizing for non-tree interconnections. ISCAS 2010: 2586-2589 - [c24]Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen:
Routability-driven RDL routing with pin reassignment. SoCC 2010: 133-138 - [c23]Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen:
Thermal via planning for temperature reduction in 3D ICs. SoCC 2010: 392-395
2000 – 2009
- 2009
- [c22]Jin-Tai Yan, Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs. ASP-DAC 2009: 588-593 - [c21]Jin-Tai Yan, Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs. ACM Great Lakes Symposium on VLSI 2009: 401-404 - [c20]Jin-Tai Yan, Zhi-Wei Chen:
Redundant wire insertion for yield improvement. ACM Great Lakes Symposium on VLSI 2009: 409-412 - [c19]Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko:
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. ISCAS 2009: 2942-2945 - [c18]Jin-Tai Yan, Zhi-Wei Chen:
Low-power multiplier design with row and column bypassing. SoCC 2009: 227-230 - [c17]Yuan-Ko Huang, Zhi-Wei Chen, Chiang Lee:
Continuous K-Nearest Neighbor Query over Moving Objects in Road Networks. APWeb/WAIM 2009: 27-38 - 2008
- [c16]Jin-Tai Yan, Zhi-Wei Chen:
Timing-driven multi-layer Steiner tree construction with obstacle avoidance. APCCAS 2008: 1684-1687 - [c15]Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee:
Timing-constrained yield-driven redundant via insertion. APCCAS 2008: 1688-1691 - [c14]Jin-Tai Yan, Zhi-Wei Chen:
Electromigration-aware rectilinear Steiner tree construction for analog circuits. APCCAS 2008: 1692-1695 - [c13]Jin-Tai Yan, Zhi-Wei Chen:
Flexible escape routing for flip-chip designs. ICECS 2008: 352-355 - [c12]Jin-Tai Yan, Zhi-Wei Chen:
Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids. ICECS 2008: 658-661 - [c11]Jin-Tai Yan, Zhi-Wei Chen, Yi-Hsiang Chou, Shun-Hua Lin, Herming Chiueh:
Thermal-driven white space redistribution for block-level floorplans. ICECS 2008: 662-665 - 2007
- [c10]Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen:
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. ICECS 2007: 717-720 - [c9]Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin:
Routability-Driven Track Routing for Coupling Capacitance Reduction. ICECS 2007: 849-852 - [c8]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. ISCAS 2007: 3395-3398 - [c7]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. SoCC 2007: 295-298 - 2006
- [c6]Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu:
Optimal Network Analysis in Hierarchical Power Quad-Grids. APCCAS 2006: 1289-1292 - [c5]Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann:
Design and implementation of a reconfigurable hardware for secure embedded systems. AsiaCCS 2006: 364 - [c4]Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen:
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. ICECS 2006: 874-877 - [c3]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven White Space Distribution for Detailed Floorplan Design. ICECS 2006: 1364-1367 - [c2]Zhi-Wei Chen, Yu-Cheng Lin, Cheng-Chin Chiang:
In this paper, an approach for deaf-people. ICPR (2) 2006: 104-107 - 2005
- [j1]Yen-Jen Oyang, Shien-Ching Hwang, Yu-Yen Ou, Chien-Yu Chen, Zhi-Wei Chen:
Data classification with radial basis function networks based on a novel kernel density estimation algorithm. IEEE Trans. Neural Networks 16(1): 225-236 (2005) - [c1]Chin-Hao Hsu, Zhi-Wei Chen, Cheng-Chin Chiang:
Region-Based Color Correction of Images. ICITA (1) 2005: 710-715
Coauthor Index
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