default search action
Jin-Tai Yan
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j41]Jin-Tai Yan:
Delay-Constrained GNR Routing With CNT-Via Insertion in Nano-Scale Designs. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 371-383 (2024) - [j40]Chia-Heng Yen, Jin-Tai Yan:
Design and analysis of sum-prediction adder. Integr. 96: 102139 (2024) - 2023
- [c76]Chia-Heng Yen, Jin-Tai Yan:
Layer-Minimization-Oriented GNR Area Routing. ICECS 2023: 1-4 - 2022
- [j39]Jin-Tai Yan:
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1090-1102 (2022) - [j38]Jin-Tai Yan:
Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2699-2713 (2022) - [j37]Jin-Tai Yan:
Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1519-1532 (2022) - 2021
- [j36]Jin-Tai Yan:
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 945-956 (2021) - [j35]Jin-Tai Yan:
Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs. IEEE Trans. Fuzzy Syst. 29(5): 1023-1036 (2021) - [j34]Jin-Tai Yan:
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1257-1270 (2021) - [j33]Jin-Tai Yan:
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1889-1902 (2021) - [c75]Jin-Tai Yan, Po-Yuan Huang, Chia-Hsun Yen:
Efficient Standard-Cell Legalization for Minimization of Total Movement. ICECS 2021: 1-4 - 2020
- [j32]Jin-Tai Yan:
Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment. ACM Trans. Design Autom. Electr. Syst. 25(2): 22:1-22:21 (2020) - [j31]Jin-Tai Yan:
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 736-749 (2020) - [j30]Jin-Tai Yan:
Delay-Constrained GNR Routing for Layer Minimization. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2356-2369 (2020) - [c74]Jin-Tai Yan, Po-Yuan Huang, Chien-Yi Wang:
Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree. TENCON 2020: 16-19
2010 – 2019
- 2019
- [j29]Jin-Tai Yan:
Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 512-525 (2019) - [j28]Jin-Tai Yan:
Single-Layer GNR Routing for Minimization of Bending Delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2099-2112 (2019) - [j27]Jin-Tai Yan:
Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing. ACM Trans. Design Autom. Electr. Syst. 24(6): 68:1-68:23 (2019) - [c73]Jin-Tai Yan, Chia-Heng Yen:
Construction of Delay-Driven GNR Routing Tree. NEWCAS 2019: 1-4 - 2018
- [j26]Jin-Tai Yan:
On-Chip Optical Channel Routing for Signal Loss Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1654-1666 (2018) - [j25]Jin-Tai Yan:
Direction-Constrained Rectangle Escape Routing. ACM Trans. Design Autom. Electr. Syst. 23(3): 34:1-34:19 (2018) - [c72]Jin-Tai Yan, Chia-Heng Yen:
Feasible Assignment of Micro-Bumps in 3D ICs. NEWCAS 2018: 296-299 - 2017
- [j24]Jin-Tai Yan:
One-Sided Net Untangling With Internal Detours for Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 952-963 (2017) - [j23]Jin-Tai Yan:
Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs. ACM Trans. Design Autom. Electr. Syst. 22(3): 45:1-45:25 (2017) - 2016
- [j22]Jin-Tai Yan:
Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1332-1344 (2016) - [j21]Jin-Tai Yan:
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs. ACM Trans. Design Autom. Electr. Syst. 21(2): 21:1-21:24 (2016) - [c71]Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen:
Cell-aware MBFF utilization for clock power reduction. ICECS 2016: 648-651 - 2015
- [j20]Jin-Tai Yan:
Length-constrained escape routing of differential pairs. Integr. 48: 158-169 (2015) - [j19]Jin-Tai Yan:
Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs. Integr. 49: 78-86 (2015) - [j18]Jin-Tai Yan:
Single-layer obstacle-aware routing for substrate interconnections. Integr. 51: 1-9 (2015) - 2014
- [j17]Jin-Tai Yan:
Fault-tolerant analysis of TMR design with noise-aware logic. Integr. 47(4): 452-460 (2014) - [c70]Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen:
Efficient micro-bump assignment for RDL routing in 3DICs. ICECS 2014: 195-198 - [c69]Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen:
Feasible region assignment of routing nets in single-layer routing. ISCAS 2014: 393-396 - 2013
- [j16]Zhi-Wei Chen, Jin-Tai Yan:
Routability-constrained multi-bit flip-flop construction for clock power reduction. Integr. 46(3): 290-300 (2013) - [c68]Jin-Tai Yan, Zhi-Wei Chen:
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ACM Great Lakes Symposium on VLSI 2013: 203-208 - [c67]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained replacement using spare cells for design changes. ACM Great Lakes Symposium on VLSI 2013: 347-348 - [c66]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout redundant wire insertion for fixing min-delay violations. ISCAS 2013: 1720-1723 - 2012
- [j15]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. Integr. 45(3): 341-347 (2012) - [j14]Jin-Tai Yan:
Resource-constrained link insertion for delay reduction. Integr. 45(4): 349-356 (2012) - [c65]Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen:
Top-down-based symmetrical buffered clock routing. ACM Great Lakes Symposium on VLSI 2012: 75-78 - [c64]Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen:
Density-reduction-oriented layer assignment for rectangle escape routing. ACM Great Lakes Symposium on VLSI 2012: 275-278 - [c63]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout OPE-predicted redundant wire insertion for clock skew minimization. ICCD 2012: 504-505 - [c62]Zhi-Wei Chen, Jin-Tai Yan:
Utilization of multi-bit flip-flops for clock power reduction. ICECS 2012: 677-680 - [c61]Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen:
Efficient assignment of inter-die signals for die-stacking SiP design. ISCAS 2012: 3254-3257 - [c60]Jin-Tai Yan, Zhi-Wei Chen:
Direction-constrained layer assignment for rectangle escape routing. SoCC 2012: 254-259 - 2011
- [j13]Jin-Tai Yan:
IO connection assignment and RDL routing for flip-chip designs. ACM Trans. Design Autom. Electr. Syst. 16(4): 47:1-47:20 (2011) - [c59]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. DATE 2011: 449-454 - [c58]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained I/O buffer placement for flip-chip designs. DATE 2011: 619-624 - [c57]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. ACM Great Lakes Symposium on VLSI 2011: 205-210 - [c56]Jin-Tai Yan, Zhi-Wei Chen:
Pre-assignment RDL routing via extraction of maximal net sequence. ICCD 2011: 65-70 - [c55]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware length-matching bus routing. ISPD 2011: 61-68 - [c54]Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen:
Simultaneous escape routing based on routability-driven net ordering. SoCC 2011: 81-86 - 2010
- [c53]Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen:
Routability-driven partitioning-based IO assignment for flip-chip designs. APCCAS 2010: 1075-1078 - [c52]Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen:
Obstacle-aware longest path using rectangular pattern detouring in routing grids. ASP-DAC 2010: 287-292 - [c51]Jin-Tai Yan, Zhi-Wei Chen:
Two-sided single-detour untangling for bus routing. DAC 2010: 206-211 - [c50]Jin-Tai Yan, Zhi-Wei Chen:
Resource-constrained timing-driven link insertion for critical delay reduction. ACM Great Lakes Symposium on VLSI 2010: 119-122 - [c49]Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen:
Ordered escape routing via routability-driven pin assignment. ACM Great Lakes Symposium on VLSI 2010: 417-422 - [c48]Zhi-Wei Chen, Jin-Tai Yan:
Routability-driven flip-flop merging process for clock power reduction. ICCD 2010: 203-208 - [c47]Jin-Tai Yan, Zhi-Wei Chen:
Low-cost low-power bypassing-based multiplier design. ISCAS 2010: 2338-2341 - [c46]Zhi-Wei Chen, Jin-Tai Yan:
Width-constrained wire sizing for non-tree interconnections. ISCAS 2010: 2586-2589 - [c45]Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen:
Routability-driven RDL routing with pin reassignment. SoCC 2010: 133-138 - [c44]Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen:
Thermal via planning for temperature reduction in 3D ICs. SoCC 2010: 392-395
2000 – 2009
- 2009
- [c43]Jin-Tai Yan, Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs. ASP-DAC 2009: 588-593 - [c42]Jin-Tai Yan, Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs. ACM Great Lakes Symposium on VLSI 2009: 401-404 - [c41]Jin-Tai Yan, Zhi-Wei Chen:
Redundant wire insertion for yield improvement. ACM Great Lakes Symposium on VLSI 2009: 409-412 - [c40]Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko:
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. ISCAS 2009: 2942-2945 - [c39]Jin-Tai Yan, Zhi-Wei Chen:
Low-power multiplier design with row and column bypassing. SoCC 2009: 227-230 - 2008
- [j12]Jin-Tai Yan:
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. ACM Trans. Design Autom. Electr. Syst. 13(2): 26:1-26:18 (2008) - [c38]Jin-Tai Yan, Zhi-Wei Chen:
Timing-driven multi-layer Steiner tree construction with obstacle avoidance. APCCAS 2008: 1684-1687 - [c37]Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee:
Timing-constrained yield-driven redundant via insertion. APCCAS 2008: 1688-1691 - [c36]Jin-Tai Yan, Zhi-Wei Chen:
Electromigration-aware rectilinear Steiner tree construction for analog circuits. APCCAS 2008: 1692-1695 - [c35]Jin-Tai Yan, Zhi-Wei Chen:
Flexible escape routing for flip-chip designs. ICECS 2008: 352-355 - [c34]Jin-Tai Yan, Zhi-Wei Chen:
Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids. ICECS 2008: 658-661 - [c33]Jin-Tai Yan, Zhi-Wei Chen, Yi-Hsiang Chou, Shun-Hua Lin, Herming Chiueh:
Thermal-driven white space redistribution for block-level floorplans. ICECS 2008: 662-665 - 2007
- [c32]Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen:
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. ICECS 2007: 717-720 - [c31]Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin:
Routability-Driven Track Routing for Coupling Capacitance Reduction. ICECS 2007: 849-852 - [c30]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. ISCAS 2007: 3395-3398 - [c29]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. SoCC 2007: 295-298 - [c28]Jin-Tai Yan, Bo-Yi Chiang:
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. VLSI Design 2007: 899-906 - 2006
- [c27]Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang:
Width and Timing-Constrained Wire Sizing for Critical Area Minimization. APCCAS 2006: 1276-1279 - [c26]Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu:
Optimal Network Analysis in Hierarchical Power Quad-Grids. APCCAS 2006: 1289-1292 - [c25]Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen:
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. ICECS 2006: 874-877 - [c24]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven White Space Distribution for Detailed Floorplan Design. ICECS 2006: 1364-1367 - [c23]Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee:
Timing-constrained yield-driven wire sizing for critical area minimization. ISCAS 2006 - [c22]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006 - [c21]Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen:
Optimal shielding insertion for inductive noise avoidance. ISCAS 2006 - [c20]Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo:
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. ISCAS 2006 - [c19]Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen:
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. VLSI Design 2006: 147-152 - 2005
- [j11]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee:
Timing-Constrained Flexibility-Driven Routing Tree Construction. IEICE Trans. Inf. Syst. 88-D(7): 1360-1368 (2005) - [c18]Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo:
LB-packing-based floorplan design on DBL representation. ICECS 2005: 1-4 - [c17]Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang:
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. ICECS 2005: 1-4 - [c16]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu:
Probabilistic congestion prediction in hierarchical quad-grid model. ISCAS (2) 2005: 1350-1353 - [c15]Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen:
Wiring area optimization in floorplan-aware hierarchical power grids. ISCAS (2) 2005: 1366-1369 - [c14]Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee:
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. ISCAS (2) 2005: 1370-1373 - [c13]Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen:
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. ISCAS (3) 2005: 2219-2222 - 2004
- [c12]Jin-Tai Yan, Shun-Hua Lin:
Timing-constrained congestion-driven global routing. ASP-DAC 2004: 683-686 - 2002
- [c11]Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen:
Printed circuit board routing and package layout codesign. APCCAS (1) 2002: 155-158 - 2000
- [j10]Jin-Tai Yan:
Three-layer bubble-sorting-based nonManhattan channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 726-734 (2000)
1990 – 1999
- 1999
- [j9]Jin-Tai Yan:
An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 163-171 (1999) - [j8]Jin-Tai Yan:
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1519-1526 (1999) - [j7]Jin-Tai Yan:
Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region. VLSI Design 10(2): 155-167 (1999) - [j6]Jin-Tai Yan:
An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement. VLSI Design 10(2): 169-176 (1999) - 1998
- [j5]Jin-Tai Yan:
Routing Space Estimation and Assignment for Macro-Cell Placement. J. Circuits Syst. Comput. 8(4): 435-446 (1998) - 1996
- [j4]Jin-Tai Yan, Pei-Yung Hsiao:
Minimizing the number of switchboxes for region definition and ordering assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 336-347 (1996) - [j3]Jin-Tai Yan, Pei-Yung Hsiao:
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment. VLSI Design 4(1): 11-16 (1996) - [c10]Jin-Tai Yan:
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. Great Lakes Symposium on VLSI 1996: 100- - [c9]Jin-Tai Yan:
A simple yet effective genetic approach for the orientation assignment on cell-based layout. VLSI Design 1996: 33-36 - 1995
- [c8]Jin-Tai Yan:
Region definition and ordering assignment with the minimization of the number of switchboxes. ASP-DAC 1995 - [c7]Jin-Tai Yan:
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. Great Lakes Symposium on VLSI 1995: 128-131 - [c6]Jin-Tai Yan:
Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. ICCD 1995: 236-241 - [c5]Jin-Tai Yan:
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. ICCD 1995: 366-371 - [c4]Jin-Tai Yan, Pei-Yung Hsiao:
A new fuzzy-clustering-based approach for two-way circuit partitioning. VLSI Design 1995: 359-364 - 1994
- [j2]Jin-Tai Yan, Pei-Yung Hsiao:
A Fuzzy Clustering Algorithm for Graph Bisection. Inf. Process. Lett. 52(5): 259-263 (1994) - [c3]Jin-Tai Yan, Pei-Yung Hsiao:
Routability crossing distribution and floating terminal assignment of T-type junction region. Great Lakes Symposium on VLSI 1994: 162-165 - [c2]Jin-Tai Yan, Pei-Yung Hsiao:
Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. ISCAS 1994: 105-108 - [c1]Paul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong-Ching Lim:
Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. ISCAS 1994: 183-186 - 1993
- [j1]Lih-Der Chang, Pei-Yung Hsiao, Jin-Tai Yan, Paul-Waie Shew:
A robust over-the-cell channel router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1592-1599 (1993)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from , , and to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:17 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint