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ORCIDIan Galton
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- affiliation: University of California, San Diego, USA
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2020 – today
- 2025
[j57]Aditi Jain
, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Asish Koruprolu, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall:
A 2.5-20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery. IEEE J. Solid State Circuits 60(3): 894-907 (2025)- 2024
- [j56]Amr I. Eissa, Enrique Alvarez-Fontecilla, Colin Weltin-Wu, Ian Galton:
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4524-4537 (2024) - [c28]Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall:
A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording. CICC 2024: 1-2 - 2023
- [j55]Subin Kim, Ian Galton:
Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4309-4322 (2023) - 2022
- [j54]Jason Remple, Andrea Panigada, Ian Galton:
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs. IEEE J. Solid State Circuits 57(2): 465-479 (2022) - [j53]Eslam Helal, Amr I. Eissa, Ian Galton:
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4993-5006 (2022) - 2021
- [j52]Eslam Helal, Enrique Alvarez-Fontecilla, Amr I. Eissa, Ian Galton:
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL. IEEE J. Solid State Circuits 56(9): 2711-2723 (2021) - [j51]Enrique Alvarez-Fontecilla, Eslam Helal, Amr I. Eissa, Ian Galton:
Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs. IEEE J. Solid State Circuits 56(10): 3191-3201 (2021) - [j50]Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton:
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 965-974 (2021) - 2020
- [j49]Derui Kong, Ian Galton:
MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3084-3098 (2020)
2010 – 2019
- 2019
- [j48]Derui Kong, Kevin Rivas-Rivera, Ian Galton:
A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error. IEEE J. Solid State Circuits 54(8): 2219-2229 (2019) - [j47]Ian Galton, Colin Weltin-Wu:
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 1-19 (2019) - [j46]Derui Kong, Ian Galton:
Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2843-2853 (2019) - [c27]Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski:
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - 2018
- [j45]Derui Kong, Ian Galton:
Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 421-433 (2018) - [j44]Enrique Alvarez-Fontecilla, Christian Venerus, Ian Galton:
Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3125-3137 (2018) - 2017
- [j43]Jason Remple, Ian Galton:
The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 14-23 (2017) - [c26]Eythan Familier, Ian Galton:
Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs. CICC 2017: 1-4 - 2016
- [j42]Eythan Familier, Ian Galton:
Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 836-847 (2016) - [j41]Christian Venerus, Jason Remple, Ian Galton:
Simplified Logic for Tree-Structure Segmented DEM Encoders. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1029-1033 (2016) - 2015
- [j40]Christian Venerus, Ian Galton:
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. IEEE J. Solid State Circuits 50(2): 450-463 (2015) - [j39]Christian Venerus, Ian Galton:
Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO". IEEE J. Solid State Circuits 50(9): 2224 (2015) - [j38]Colin Weltin-Wu, Guobi Zhao, Ian Galton:
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. IEEE J. Solid State Circuits 50(12): 2988-3002 (2015) - [j37]Colin Weltin-Wu, Eythan Familier, Ian Galton:
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2013-2023 (2015) - [j36]Christian Venerus, Ian Galton:
Quantization Noise Cancellation for FDC-Based Fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1119-1123 (2015) - [c25]Colin Weltin-Wu, Guobi Zhao, Ian Galton:
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. ISSCC 2015: 1-3 - 2013
- [j35]Gerry Taylor, Ian Galton:
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB. IEEE J. Solid State Circuits 48(4): 983-995 (2013) - [j34]Nevena Rakuljic, Ian Galton:
Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 593-602 (2013) - [j33]Christian Venerus, Ian Galton:
Delta-Sigma FDC Based Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1274-1285 (2013) - [j32]Eythan Familier, Ian Galton:
A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones. IEEE Trans. Signal Process. 61(16): 4172-4180 (2013) - [j31]Eythan Familier, Christian Venerus, Ian Galton:
A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones. IEEE Trans. Signal Process. 61(17): 4270-4283 (2013) - 2012
- [c24]Gerry Taylor, Ian Galton:
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB. VLSIC 2012: 166-167 - 2011
- [j30]Gerry Taylor, Ian Galton:
Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261]. IEEE J. Solid State Circuits 46(5): 1231 (2011) - [j29]Kevin J. Wang, Ian Galton:
A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 264-275 (2011) - 2010
- [j28]Gerry Taylor, Ian Galton:
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC. IEEE J. Solid State Circuits 45(12): 2634-2646 (2010) - [j27]Ian Galton:
Why Dynamic-Element-Matching DACs Work. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 69-74 (2010) - [j26]Nevena Rakuljic, Ian Galton:
Tree-Structured DEM DACs with Arbitrary Numbers of Levels. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(2): 313-322 (2010) - [c23]Gerry Taylor, Ian Galton:
A mostly digital variable-rate continuous-time ADC ΔΣ modulator. ISSCC 2010: 298-299 - [c22]Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget:
CMOS phase-locked loops for frequency synthesis. ISSCC 2010: 521
2000 – 2009
- 2009
- [j25]Andrea Panigada, Ian Galton:
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction. IEEE J. Solid State Circuits 44(12): 3314-3328 (2009) - [c21]Andrea Panigada, Ian Galton:
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction. ISSCC 2009: 162-163 - [c20]Ian Galton:
Low-voltage analog and mixed-signal CMOS circuit design. ISSCC 2009: 502 - 2008
- [j24]Kok Lim Chan, Jianyu Zhu, Ian Galton:
Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs. IEEE J. Solid State Circuits 43(9): 2067-2078 (2008) - [j23]Kevin J. Wang, Ashok Swaminathan, Ian Galton:
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL. IEEE J. Solid State Circuits 43(12): 2787-2797 (2008) - [j22]Kok Lim Chan, Nevena Rakuljic, Ian Galton:
Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3383-3392 (2008) - [c19]Kevin J. Wang, Ashok Swaminathan, Ian Galton:
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. ISSCC 2008: 342-343 - [c18]Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders:
Short Course. ISSCC 2008: 648-649 - 2007
- [j21]Ashok Swaminathan, Kevin J. Wang, Ian Galton:
A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation. IEEE J. Solid State Circuits 42(12): 2639-2650 (2007) - [j20]Sudhakar Pamarti, Jared Welz, Ian Galton:
Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 492-503 (2007) - [j19]Sudhakar Pamarti, Ian Galton:
LSB Dithering in MASH Delta-Sigma D/A Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(4): 779-790 (2007) - [j18]Ashok Swaminathan, Andrea Panigada, Elias Masry, Ian Galton:
A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion. IEEE Trans. Signal Process. 55(11): 5382-5394 (2007) - [c17]Ashok Swaminathan, Kevin J. Wang, Ian Galton:
A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation. ISSCC 2007: 302-604 - [c16]Ian Galton, Matt Miller, Robert Bogdan Staszewski, Bram Nauta, Michiel Steyaert:
Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. ISSCC 2007: 635-636 - 2006
- [j17]Andrea Panigada, Ian Galton:
Digital Background Correction of Harmonic Distortion in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1885-1895 (2006) - [c15]Kok Lim Chan, Ian Galton:
A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching. ISSCC 2006: 2390-2399 - 2005
- [j16]Sudhakar Pamarti, Lars C. Jansson, Ian Galton:
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". IEEE J. Solid State Circuits 40(2): 559 (2005) - 2004
- [j15]Sudhakar Pamarti, Lars C. Jansson, Ian Galton:
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. IEEE J. Solid State Circuits 39(1): 49-62 (2004) - [j14]Sheng Ye, Ian Galton:
Techniques for phase noise suppression in recirculating DLLs. IEEE J. Solid State Circuits 39(8): 1222-1230 (2004) - [j13]Eric Siragusa, Ian Galton:
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. IEEE J. Solid State Circuits 39(12): 2126-2138 (2004) - [j12]Jared Welz, Ian Galton:
A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter. IEEE Trans. Inf. Theory 50(4): 593-607 (2004) - 2003
- [j11]Sudhakar Pamarti, Ian Galton:
Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 829-838 (2003) - [j10]Ian Galton:
Editorial. IEEE Trans. Circuits Syst. II Express Briefs 50(12): 905 (2003) - [c14]Sheng Ye, Lars C. Jansson, Ian Galton:
Techniques for in-band phase noise suppression in re-circulating DLLs. CICC 2003: 297-300 - 2002
- [j9]Jorge Grilo, Ian Galton, Kevin J. Wang, Raymond Montemayor:
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. IEEE J. Solid State Circuits 37(3): 271-278 (2002) - [j8]Sheng Ye, Lars C. Jansson, Ian Galton:
A multiple-crystal interface PLL with VCO realignment to reduce phase noise. IEEE J. Solid State Circuits 37(12): 1795-1803 (2002) - [c13]Jared Welz, Ian Galton:
A necessary and sufficient condition for mismatch shaping in multi-bit DACs. ISCAS (1) 2002: 105-108 - [c12]Asaf Fishov, Eric Siragusa, Jared Welz, Eric Fogleman, Ian Galton:
Segmented mismatch-shaping D/A conversion. ISCAS (4) 2002: 679-682 - 2001
- [j7]Eric Fogleman, Jared Welz, Ian Galton:
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC. IEEE J. Solid State Circuits 36(3): 339-348 (2001) - [c11]Jorge Grilo, Ian Galton, Kevin Wang, Raymond Montemayor:
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. CICC 2001: 23-26 - [c10]Jared Welz, Ian Galton:
The mismatch-noise PSD from a tree-structured DAC in a second-order ΔΣ modulator with a midscale input. ICASSP 2001: 2625-2628 - 2000
- [j6]Eric Fogleman, Ian Galton, William Huff, Henrik Jensen:
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR. IEEE J. Solid State Circuits 35(3): 297-307 (2000) - [c9]Eric Fogleman, Jared Welz, Ian Galton:
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC. CICC 2000: 17-20
1990 – 1999
- 1999
- [c8]Eric Fogleman, Ian Galton, William Huff, Henrik Jensen:
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD. CICC 1999: 121-124 - [c7]Eric Fogleman, Ian Galton, Henrik Jensen:
A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs. ISCAS (2) 1999: 290-293 - [c6]Eric Fogleman, Ian Galton, Henrik Jensen:
An area-efficient differential input ADC with digital common mode rejection. ISCAS (2) 1999: 347-350 - 1998
- [j5]Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez:
A Nyquist-rate delta-sigma A/D converter. IEEE J. Solid State Circuits 33(1): 45-52 (1998) - [j4]Ian Galton, William Huff, Paolo Carbone, Eric Siragusa:
A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal. IEEE J. Solid State Circuits 33(12): 2042-2053 (1998) - 1995
- [c5]Ian Galton:
A Practical Second-Order Delta-Digma Frequency-to-Digital Converter. ISCAS 1995: 5-8 - [c4]Henrik T. Jensen, Ian Galton:
A Robust Parallel Delta-Sigma A/D Converter Architecture. ISCAS 1995: 1340-1343 - 1994
- [j3]Ian Galton:
Granular quantization noise in a class of delta-sigma modulators. IEEE Trans. Inf. Theory 40(3): 848-859 (1994) - [c3]Ian Galton:
Higher-Order Delta-Sigma Frequency to Digital Conversion. ISCAS 1994: 441-444 - 1993
- [j2]Ian Galton:
Granular quantization noise in the first-order delta-sigma modulator. IEEE Trans. Inf. Theory 39(6): 1944-1956 (1993) - [c2]Ian Galton, George Zimmerman:
Combined RF Phase Extraction and Digitalization. ISCAS 1993: 1104-1107 - [c1]Ian Galton:
One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion. ISCAS 1993: 1310-1313
1980 – 1989
- 1989
- [j1]Ian Galton:
An efficient three-point arc algorithm. IEEE Computer Graphics and Applications 9(6): 44-49 (1989)
Coauthor Index
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