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ORCIDYici Cai
Person information
- affiliation: Tsinghua University, Department of Computer Science and Technology, Beijing, China
- affiliation (PhD 2007): University of Science and Technology of China, Hefei, China
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2020 – today
- 2023
[j81]Jianwang Zhai
, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 243-256 (2023)- [j80]Jianwang Zhai, Yici Cai:
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1727-1739 (2023) - [c171]Jianwang Zhai, Yici Cai, Bei Yu:
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC 2023: 302-307 - [c170]Haoyi Wang, Qiang Zhou, Yici Cai:
Static Probability Analysis Guided RTL Hardware Trojan Test Generation. ASP-DAC 2023: 510-515 - 2022
- [j79]Rui Hao, Yici Cai, Qiang Zhou:
Intelligent and kernelized placement: A survey. Integr. 86: 44-50 (2022) - [j78]Lin Li, Yici Cai, Qiang Zhou:
A survey on machine learning-based routing for VLSI physical design. Integr. 86: 51-56 (2022) - [c169]Wenyan Wu, Yici Cai, Qiang Zhou:
TransMarker: A Pure Vision Transformer for Facial Landmark Detection. ICPR 2022: 3580-3587 - 2021
- [j77]Haoyi Wang, Yici Cai, Qiang Zhou:
A game theory approach for RTL security verification resources allocation. CCF Trans. High Perform. Comput. 3(1): 57-69 (2021) - [j76]Jing Wang, Yici Cai, Qiang Zhou:
Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks. J. Comput. Sci. Technol. 36(5): 1133-1144 (2021) - [j75]Jianwang Zhai, Yici Cai, Qiang Zhou:
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1571-1575 (2021) - [c168]Wenyan Wu, Yici Cai, Qiang Zhou:
SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data. FG 2021: 1-8 - [c167]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD 2021: 1-9 - [c166]Lin Li, Yici Cai, Qiang Zhou:
An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. ISCAS 2021: 1-5 - [c165]Jing Wang, Yici Cai, Qiang Zhou:
A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. ISCAS 2021: 1-5 - 2020
- [j74]Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li:
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 613-625 (2020)
2010 – 2019
- 2019
- [j73]Wenyan Wu, Xingzhe Wu, Yici Cai, Qiang Zhou:
Deep coupling neural network for robust facial landmark detection. Comput. Graph. 82: 286-294 (2019) - [j72]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integr. 67: 108-120 (2019) - [j71]Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou:
A high-level information flow tracking method for detecting information leakage. Integr. 69: 393-399 (2019) - [j70]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1844-1857 (2019) - [c164]Jing Wang, Yici Cai, Ming Yan, Qiang Zhou:
Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. ISCAS 2019: 1-5 - 2018
- [j69]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Spear and Shield: Evolution of Integrated Circuit Camouflaging. J. Comput. Sci. Technol. 33(1): 42-57 (2018) - [j68]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 217-230 (2018) - [j67]Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai:
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1157-1170 (2018) - [j66]Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai:
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3042-3055 (2018) - [c163]Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang:
ASAX: Automatic security assertion extraction for detecting Hardware Trojans. ASP-DAC 2018: 84-89 - [c162]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. ASP-DAC 2018: 259-264 - [c161]Chenguang Wang, Yici Cai, Qiang Zhou:
HLIFT: A high-level information flow tracking method for detecting hardware Trojans. ASP-DAC 2018: 727-732 - [c160]Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou:
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CVPR 2018: 2129-2138 - [c159]Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou:
Electromigration Design Rule aware Global and Detailed Routing Algorithm. ACM Great Lakes Symposium on VLSI 2018: 267-272 - [c158]Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou:
Electromagnetic equalizer: an active countermeasure against EM side-channel attack. ICCAD 2018: 112 - [c157]Jia Wei, Qiang Zhou, Yici Cai:
Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks. ICNC 2018: 156-160 - [i1]Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou:
Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CoRR abs/1805.10483 (2018) - 2017
- [j65]Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1488-1499 (2017) - [c156]Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC 2017: 524-529 - [c155]Yunxing Xin, Yongqiang Chen, Li Jin, Yici Cai, Ling Feng:
TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy. BigData Congress 2017: 431-434 - [c154]Xiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang:
Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks. DATE 2017: 1727-1732 - [c153]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. ACM Great Lakes Symposium on VLSI 2017: 345-350 - [c152]Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai:
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI 2017: 447-450 - [c151]Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang:
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD 2017: 305-312 - [c150]Chenguang Wang, Yici Cai, Qiang Zhou:
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. ICCD 2017: 321-328 - [c149]Xueyan Wang, Yici Cai, Qiang Zhou:
Cell spreading optimization for force-directed global placers. ISCAS 2017: 1-4 - [c148]Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou:
An Effective Power Grid Optimization Approach for the Electromigration Reliability. ISVLSI 2017: 453-458 - 2016
- [j64]Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai:
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1283-1296 (2016) - [c147]Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC 2016: 587-592 - [c146]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. ACM Great Lakes Symposium on VLSI 2016: 87-92 - [c145]Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu:
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI 2016: 133-136 - [c144]Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai:
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD 2016: 103 - [c143]Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu:
An efficient framework for configurable RO PUF. ISCAS 2016: 742-745 - [c142]Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
Is the Secure IC camouflaging really secure? ISCAS 2016: 1710-1713 - 2015
- [j63]Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho:
Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test 32(6): 60-68 (2015) - [j62]Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
SIAR: Customized real-time interactive router for analog circuits. Integr. 48: 170-182 (2015) - [j61]Chao Deng, Yici Cai, Qiang Zhou:
Register Clustering Methodology for Low Power Clock Tree Synthesis. J. Comput. Sci. Technol. 30(2): 391-403 (2015) - [j60]Zhongdong Qi, Yici Cai, Qiang Zhou:
Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths. J. Comput. Sci. Technol. 30(3): 614-628 (2015) - [j59]Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 142-155 (2015) - [j58]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2617-2628 (2015) - [c141]Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai:
Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC 2015: 779-784 - [c140]Hailong Yao, Tsung-Yi Ho, Yici Cai:
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC 2015: 142:1-142:6 - [c139]Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai:
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD 2015: 49-56 - [c138]Chao Deng, Yici Cai, Qiang Zhou:
Fast synthesis of low power clock trees based on register clustering. ISQED 2015: 303-309 - 2014
- [j57]Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang:
Fast and scalable parallel layout decomposition in double patterning lithography. Integr. 47(2): 175-183 (2014) - [j56]Yong-Qiang Lv, Qiang Zhou, Yici Cai, Gang Qu:
Trusted Integrated Circuits: The Problem and Challenges. J. Comput. Sci. Technol. 29(5): 918-928 (2014) - [j55]Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. 45(6): 604-612 (2014) - [j54]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 899-912 (2014) - [j53]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2103-2116 (2014) - [c137]Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang:
Time-domain performance bound analysis for analog and interconnect circuits considering process variations. ASP-DAC 2014: 455-460 - [c136]Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen:
VFGR: A very fast parallel global router with accurate congestion modeling. ASP-DAC 2014: 525-530 - [c135]Wei Zhao, Yici Cai, Jianlei Yang:
Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC 2014: 861-866 - [c134]Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC 2014: 143:1-143:6 - [c133]Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou:
Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT 2014: 161-166 - [c132]Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li:
MCFRoute: a detailed router based on multi-commodity flow method. ICCAD 2014: 397-404 - [c131]Zhongdong Qi, Yici Cai, Qiang Zhou:
Accurate prediction of detailed routing congestion using supervised data learning. ICCD 2014: 97-103 - [c130]Chao Deng, Yici Cai, Qiang Zhou:
A register clustering algorithm for low power clock tree synthesis. ISCAS 2014: 389-392 - [c129]Ziyang Qi, Kun Ma, Qiang Zhou, Yici Cai:
RSMT construction algorithm based on Congestion-Oriented Flexibility. LASCAS 2014: 1-4 - 2013
- [j52]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang:
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. 46(1): 1-9 (2013) - [c128]Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou:
Analog routing considering min-area constraint. ASICON 2013: 1-4 - [c127]Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou:
A new splitting graph construction algorithm for SIAR router. ASICON 2013: 1-4 - [c126]Wei Zhao, Yici Cai, Jianlei Yang:
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC 2013: 163-168 - [c125]Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai:
Performance bound and yield analysis for analog circuits under process variations. ASP-DAC 2013: 761-766 - [c124]Zhongdong Qi, Yici Cai, Qiang Zhou:
Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model. CAD/Graphics 2013: 74-80 - [c123]Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu:
Design and Implementation of a Delay-Based PUF for FPGA IP Protection. CAD/Graphics 2013: 107-114 - [c122]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
Selected inversion for vectorless power grid verification by exploiting locality. ICCD 2013: 257-263 - [c121]Zihao Chen, Hailong Yao, Yici Cai:
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED 2013: 566-571 - 2012
- [c120]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie:
Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC 2012: 47-52 - [c119]Hailong Yao, Yici Cai, Qiang Gao:
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC 2012: 157-162 - [c118]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush : Efficient transient simulation for power grid analysis. ICCAD 2012: 653-659 - [c117]Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai:
A DyadicCluster method used for nonlinear placement. ISQED 2012: 418-423 - 2011
- [j51]Qiang Zhou, Jin Shi, Bin Liu, Yici Cai:
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 638-646 (2011) - [c116]Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai:
A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD 2011: 91-96 - [c115]Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI 2011: 199-204 - [c114]Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai:
SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI 2011: 367-370 - [c113]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: A linear simulator for power grid. ICCAD 2011: 482-487 - [c112]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Fast poisson solver preconditioned method for robust power grid analysis. ICCAD 2011: 531-536 - [c111]Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai:
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED 2011: 36-41 - [c110]Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao:
A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED 2011: 621-626 - [c109]Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai:
Statistical full-chip dynamic power estimation considering spatial correlations. ISQED 2011: 677-682 - [c108]Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai:
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI 2011: 212-217 - 2010
- [j50]Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. Integr. 43(1): 156-165 (2010) - [j49]Yici Cai, Jin Shi, Shuai Li:
Optimization of via distribution and stacked via in multi-layered P/G networks. Integr. 43(3): 318-325 (2010) - [j48]Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong:
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 153-157 (2010) - [j47]Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen:
Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1556-1566 (2010) - [j46]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1639-1648 (2010) - [c107]Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai:
Efficient model reduction of interconnects via double gramians approximation. ASP-DAC 2010: 25-30 - [c106]Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Efficient power grid integrity analysis using on-the-fly error check and reduction. ASP-DAC 2010: 763-768 - [c105]Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian:
An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. CSCWD 2010: 701-706 - [c104]Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu:
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE 2010: 1369-1372 - [c103]Jin Shi, Yici Cai:
Scaling power/ground solvers on multi-core with memory bandwidth awareness. ACM Great Lakes Symposium on VLSI 2010: 21-26 - [c102]Qiang Gao, Yin Shen, Yici Cai, Hailong Yao:
Analog circuit shielding routing algorithm based on net classification. ISLPED 2010: 123-128 - [c101]Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu:
Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED 2010: 62-68
2000 – 2009
- 2009
- [j45]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. 52(8): 1466-1475 (2009) - [j44]Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong:
An MTCMOS technology for low-power physical design. Integr. 42(3): 340-345 (2009) - [c100]Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166 - [c99]Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics 2009: 190-194 - [c98]Yun Huang, Qiang Zhou, Yici Cai, Haixia Yan:
A thermal-driven force-directed floorplanning algorithm for 3D ICs. CAD/Graphics 2009: 497-502 - [c97]Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang:
GPU friendly fast Poisson solver for structured power grid network analysis. DAC 2009: 178-183 - [c96]Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles:
An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195 - [c95]Jinpeng Zhao, Qiang Zhou, Yici Cai:
Fast congestion-aware timing-driven placement for island FPGA. DDECS 2009: 24-27 - [c94]Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia:
Decoupling capacitance efficient placement for reducing transient power supply noise. ICCAD 2009: 745-751 - [c93]Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong:
Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510 - 2008
- [j43]Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang:
Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. 51(2): 213-224 (2008) - [j42]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 595-603 (2008) - [j41]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2084-2090 (2008) - [j40]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3443-3450 (2008) - [j39]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3783-3792 (2008) - [j38]Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong:
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2(1): 2-15 (2008) - [j37]Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. 41(1): 153-160 (2008) - [j36]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. 41(3): 426-438 (2008) - [j35]Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1996-2006 (2008) - [j34]Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 36-40 (2008) - [j33]Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 2064-2075 (2008) - [c92]Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong:
Wire density driven top-down global placement for CMP variation control. APCCAS 2008: 1676-1679 - [c91]Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375 - [c90]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Heuristic power/ground network and floorplan co-design method. ASP-DAC 2008: 617-622 - [c89]Shuai Li, Jin Shi, Yici Cai, Xianlong Hong:
Vertical via design techniques for multi-layered P/G networks. ASP-DAC 2008: 623-628 - [c88]Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562 - [c87]Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI 2008: 255-260 - [c86]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Gate planning during placement for gated clock network. ICCD 2008: 128-133 - [c85]Weixiang Shen, Yici Cai, Xianlong Hong:
Leakage power optimization for clock network using dual-Vth technology. ISCAS 2008: 2769-2772 - [c84]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design. ISPD 2008: 182-189 - [c83]Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED 2008: 357-360 - [c82]Yibo Wang, Yici Cai, Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226 - [c81]Yanming Jia, Yici Cai, Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI 2008: 10-15 - 2007
- [j32]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 267-273 (2007) - [j31]Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 1028-1037 (2007) - [j30]Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu:
An efficient quadratic placement based on search space traversing technology. Integr. 40(3): 253-260 (2007) - [j29]Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. 40(4): 516-524 (2007) - [j28]Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong:
A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22(5): 653-660 (2007) - [j27]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong:
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 680-692 (2007) - [c80]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang:
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372 - [c79]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC 2007: 666-671 - [c78]Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756 - [c77]Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang:
Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics 2007: 332-337 - [c76]Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513 - [c75]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI 2007: 31-36 - [c74]Xinjie Wei, Yici Cai, Xianlong Hong:
Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI 2007: 473-476 - [c73]Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575 - [c72]Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53 - [c71]Xinjie Wei, Yici Cai, Xianlong Hong:
Effective Acceleration of Iterative Slack Distribution Process. ISCAS 2007: 1077-1080 - [c70]Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai:
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS 2007: 2040-2043 - [c69]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304 - [c68]Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED 2007: 350-355 - [c67]Hailong Yao, Yici Cai, Xianlong Hong:
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI 2007: 239-244 - [c66]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388 - 2006
- [j26]Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu:
Time-domain analysis methodology for large-scale RLC circuits and its applications. Sci. China Ser. F Inf. Sci. 49(5): 665-680 (2006) - [j25]Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong:
Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. 21(6): 913-921 (2006) - [j24]Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2402-2412 (2006) - [j23]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1007-1011 (2006) - [j22]Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo:
Power/Ground Network Optimization Considering Decap Leakage Currents. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1012-1016 (2006) - [j21]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1148-1152 (2006) - [j20]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j19]Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong:
Legitimate Skew Clock Routing with Buffer Insertion. J. VLSI Signal Process. 42(2): 107-116 (2006) - [c65]Xianlong Hong, Yici Cai, Hailong Yao, Duo Li:
DFM-aware Routing for Yield Enhancement. APCCAS 2006: 1091-1094 - [c64]Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong:
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS 2006: 1635-1638 - [c63]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC 2006: 582-587 - [c62]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong:
Efficient early stage resonance estimation techniques for C4 package. ASP-DAC 2006: 826-831 - [c61]Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai:
Efficient process-hotspot detection using range pattern matching. ICCAD 2006: 625-632 - [c60]Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006 - [c59]Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu:
High performance clock routing in X-architecture. ISCAS 2006 - [c58]Yibo Wang, Yici Cai, Xianlong Hong:
Performance and power aware buffered tree construction. ISCAS 2006 - [c57]Hailong Yao, Yici Cai, Xianlong Hong:
Congestion-driven W-shape multilevel full-chip routing framework. ISCAS 2006 - [c56]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong:
A novel low-power physical design methodology for MTCMOS. ISCAS 2006 - [c55]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong:
High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD 2006: 108-113 - [c54]Xinjie Wei, Yici Cai, Xianlong Hong:
Clock Skew Scheduling Under Process Variations. ISQED 2006: 237-242 - [c53]Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED 2006: 272-277 - 2005
- [j18]Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu:
Reliable buffered clock tree routing algorithm with process variation tolerance. Sci. China Ser. F Inf. Sci. 48(5): 670-680 (2005) - [j17]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1565-1572 (2005) - [j16]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1964-1970 (2005) - [j15]Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005) - [j14]Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong:
Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. 20(2): 224-230 (2005) - [j13]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20(2): 231-236 (2005) - [j12]Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong:
Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. 20(6): 901-906 (2005) - [c52]Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98 - [c51]Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102 - [c50]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. ASP-DAC 2005: 588-593 - [c49]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738 - [c48]Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu:
Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093 - [c47]Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175 - [c46]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181 - [c45]Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI 2005: 143-146 - [c44]Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai:
A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI 2005: 221-224 - [c43]Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong:
A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) 2005: 181-184 - [c42]Yici Cai, Yibo Wang, Xianlong Hong:
A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96 - [c41]Yiqian Zhang, Xianlong Hong, Yici Cai:
An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. ISCAS (1) 2005: 97-100 - [c40]Xinjie Wei, Yici Cai, Xianlong Hong:
Zero skew clock routing with tree topology construction using simulated annealing method. ISCAS (1) 2005: 101-104 - [c39]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) 2005: 1871-1874 - [c38]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233 - [c37]Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547 - [c36]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS 2005: 257-266 - [c35]Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS 2005: 318-328 - [c34]Yibo Wang, Yici Cai, Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96 - 2004
- [j11]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j10]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j9]Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1086-1094 (2004) - [j8]Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 228-233 (2004) - [j7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c33]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510 - [c32]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c31]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - [c30]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349 - [c29]Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84 - [c28]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) 2004: 85-88 - [c27]Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai:
Crosstalk driven routing resource assignment. ISCAS (5) 2004: 89-92 - [c26]Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou:
Algorithm for yield driven correction of layout. ISCAS (5) 2004: 241-245 - [c25]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) 2004: 297-300 - [c24]Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong:
Quick and effective buffered legitimate skew clock routing. ISCAS (5) 2004: 337-340 - [c23]Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong:
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68 - [c22]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441 - 2003
- [j6]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3158-3167 (2003) - [j5]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integr. 35(2): 69-84 (2003) - [j4]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
FaSa: A Fast and Stable Quadratic Placement Algorithm. J. Comput. Sci. Technol. 18(3): 318-324 (2003) - [c21]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c20]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
A path-based timing-driven quadratic placement algorithm. ASP-DAC 2003: 745-748 - [c19]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC 2003: 834-839 - [c18]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. ASP-DAC 2003: 847-850 - [c17]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c16]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c15]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c14]Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai:
Combining clustering and partitioning in quadratic placement. ISCAS (4) 2003: 720-723 - [c13]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - 2002
- [j3]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior. Sci. China Ser. F Inf. Sci. 45(4): 310-320 (2002) - [j2]Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) - [c12]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu:
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) 2002: 165-168 - [c11]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - [c10]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. ASP-DAC/VLSI Design 2002: 473-478 - 2001
- [j1]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [c9]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c8]Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao:
A new congestion-driven placement algorithm based on cell inflation. ASP-DAC 2001: 605-608 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 - [c6]Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD 2001: 153-157 - 2000
- [c5]Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong:
Area routing oriented hierarchical corner stitching with partial bin. ASP-DAC 2000: 105-110 - [c4]Hong Yu, Xianlong Hong, Yici Cai:
MMP: a novel placement algorithm for combined macro block and standard cell layout design. ASP-DAC 2000: 271-276 - [c3]Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12
1990 – 1999
- 1999
- [c2]Haiyun Bao, Xianlong Hong, Yici Cai:
A New Global Routing Algorithm Independent Of Net Ordering. ASP-DAC 1999: 245-248 - [c1]Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai:
A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC 1999: 249-252
Coauthor Index
[j48] [j46] [j45] [j44] [c100] [c99] [c96] [c93] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [j32] [j31] [j30] [j29] [j28] [j27] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [j11] [j10] [j9] [j8] [j7] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j6] [j5] [j4] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j3] [j2] [c12] [c11] [c10] [j1] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
[j81] [c170] [j79] [j78] [c169] [j77] [j76] [j75] [c168] [c167] [c166] [c165] [j73] [j72] [j71] [j70] [c164] [j69] [j68] [c163] [c162] [c161] [c160] [c159] [c158] [c157] [i1] [c153] [c151] [c150] [c149] [c148] [c146] [c145] [c143] [c142] [j62] [j61] [j60] [j59] [j58] [c138] [j56] [j55] [j54] [j53] [c136] [c133] [c132] [c131] [c130] [c129] [j52] [c128] [c127] [c124] [c123] [c122] [c120] [c118] [c117] [j51] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c108] [j48] [c105] [c104] [c101] [j44] [c99] [c98] [c95] [c94] [c93] [j43] [j41] [c92] [c91] [c88] [c87] [c83] [j32] [j30] [j28] [c80] [c79] [c73] [c70] [c68] [j25] [j23] [j21] [j20] [c64] [c63] [c60] [c56] [j17] [j16] [j15] [j13] [j12] [c52] [c51] [c50] [c46] [c45] [c44] [c43] [c39] [c38] [c36] [c30] [c29] [c28] [c27] [c26] [c25]
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-04 20:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
