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ORCIDPrithviraj Banerjee
Prith Banerjee
Person information
- affiliation: Northwestern University, Illinois, USA
- award (1987): Presidential Young Investigator Award
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2020 – today
- 2024
[i3]Prithviraj Banerjee, Sindi Shkodrani, Pierre Moulon, Shreyas Hampali, Fan Zhang, Jade Fountain, Edward Miller, Selen Basol, Richard A. Newcombe, Robert Wang, Jakob Julian Engel, Tomas Hodan:
Introducing HOT3D: An Egocentric Dataset for 3D Hand and Object Tracking. CoRR abs/2406.09598 (2024)- [i2]Prithviraj Banerjee, Sindi Shkodrani, Pierre Moulon, Shreyas Hampali, Shangchen Han, Fan Zhang, Linguang Zhang, Jade Fountain, Edward Miller, Selen Basol, Richard A. Newcombe, Robert Wang, Jakob Julian Engel, Tomas Hodan:
HOT3D: Hand and Object Tracking in 3D from Egocentric Multi-View Videos. CoRR abs/2411.19167 (2024) - 2022
- [j82]Matt Adams
, Xiao Li, Lucas Boucinha, Sameer S. Kher, Prith Banerjee, Jose-Luis Gonzalez:
Hybrid Digital Twins: A Primer on Combining Physics-Based and Data Analytics Approaches. IEEE Softw. 39(2): 47-52 (2022) - [c213]Jiuhong Xiao, Lavisha Aggarwal, Prithviraj Banerjee, Manoj Aggarwal, Gerard Medioni:
Identity Preserving Loss for Learned Image Compression. CVPR Workshops 2022: 516-525 - [i1]Jiuhong Xiao, Lavisha Aggarwal, Prithviraj Banerjee, Manoj Aggarwal, Gerard Medioni:
Identity Preserving Loss for Learned Image Compression. CoRR abs/2204.10869 (2022)
2010 – 2019
- 2014
- [c212]Prithviraj Banerjee, Ram Nevatia:
Multi-state Discriminative Video Segment Selection for Complex Event Classification. ACCV (5) 2014: 162-177 - [c211]Prithviraj Banerjee, Ramakant Nevatia:
Pose Filter Based Hidden-CRF Models for Activity Detection. ECCV (2) 2014: 711-726 - 2012
- [j81]Prithviraj Banerjee, Chandrakant D. Patel, Cullen E. Bash, Amip Shah, Martin F. Arlitt:
Towards a net-zero data center. ACM J. Emerg. Technol. Comput. Syst. 8(4): 27:1-27:39 (2012) - [j80]Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
On a Technique for Transparently Empowering Classical Compiler Optimizations on Multithreaded Code. ACM Trans. Program. Lang. Syst. 34(2): 9:1-9:42 (2012) - [c210]Prithviraj Banerjee, Ramakant Nevatia:
Pose based activity recognition using Multiple Kernel learning. ICPR 2012: 445-448 - 2011
- [j79]Prith Banerjee, Rich Friedrich, Cullen E. Bash, Patrick Goldsack, Bernardo A. Huberman, John Manley, Chandrakant D. Patel, Parthasarathy Ranganathan, Alistair C. Veitch:
Everything as a Service: Powering the New Information Economy. Computer 44(3): 36-43 (2011) - [c209]Lei Gao, Gaurav Mittal, David Zaretsky, Prith Banerjee:
Resource optimization and deadlock prevention while generating streaming architectures from ordinary programs. AHS 2011: 9-16 - [c208]Prithviraj Banerjee, Ram Nevatia:
Learning neighborhood cooccurrence statistics of sparse features for human activity recognition. AVSS 2011: 212-217 - [c207]Dhruva R. Chakrabarti, Prithviraj Banerjee, Hans-Juergen Boehm, Pramod G. Joisha, Robert S. Schreiber:
The runtime abort graph and its application to software transactional memory optimization. CGO 2011: 42-53 - [c206]Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code. POPL 2011: 623-636 - 2010
- [j78]Prith Banerjee, Rich Friedrich, Lueny Morell:
Open Innovation at HP Labs. Computer 43(11): 88-90 (2010) - [c205]Prithviraj Banerjee, Ram Nevatia:
Dynamics Based Trajectory Segmentation for UAV videos. AVSS 2010: 345-352 - [c204]Prith Banerjee:
An Intelligent IT Infrastructure for the Future. ICDCN 2010: 1 - [c203]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
Automatic Generation of Stream Descriptors for Streaming Architectures. ICPP 2010: 307-312 - [c202]Pradeep Natarajan, Prithviraj Banerjee, Ram Nevatia:
Accurate person tracking through changing poses for multi-view action recognition. ICVGIP 2010: 155-161
2000 – 2009
- 2009
- [c201]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC 2009: 636-641 - [c200]Prith Banerjee, Chandrakant D. Patel, Cullen E. Bash, Parthasarathy Ranganathan:
Sustainable data centers: enabled by supply and demand side management. DAC 2009: 884-887 - [c199]Gaurav Mittal, David Zaretsky, Prithviraj Banerjee:
Streaming implementation of a sequential decompression algorithm on an FPGA. FPGA 2009: 283 - [c198]Prith Banerjee:
An intelligent IT infrastructure for the future. HPCA 2009: 3-4 - [c197]Lei Gao, Gaurav Mittal, David Zaretsky, Dan Schonfeld, Prithviraj Banerjee:
An Automated Algorithm to Generate Stream Programs. ISCAS 2009: 1505-1508 - [c196]David Zaretsky, Gaurav Mittal, Prithviraj Banerjee:
Streaming Implementation of the ZLIB Decoder Algorithm on an FPGA. ISCAS 2009: 2329-2332 - [c195]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
A software pipelining algorithm in high-level synthesis for FPGA architectures. ISQED 2009: 297-302 - 2008
- [c194]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC 2008: 42-48 - [c193]Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee:
State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT 2008: 11-20 - 2007
- [j77]Pramod G. Joisha, Prithviraj Banerjee:
A translator system for the MATLAB language. Softw. Pract. Exp. 37(5): 535-578 (2007) - [j76]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 447-455 (2007) - [j75]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
An Overview of a Compiler for Mapping Software Binaries to Hardware. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1177-1190 (2007) - [c192]Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee:
Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485 - [c191]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. ISQED 2007: 595-601 - 2006
- [j74]Tianyi Jiang, Xiaoyong Tang, Prith Banerjee:
Macro-models for high-level area and power estimation on FPGAs. Int. J. Simul. Process. Model. 2(1/2): 12-19 (2006) - [j73]Pramod G. Joisha, Prithviraj Banerjee:
An algebraic array shape inference system for MATLAB. ACM Trans. Program. Lang. Syst. 28(5): 848-907 (2006) - [c190]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623 - [c189]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. VLSI Design 2006: 465-468 - 2005
- [j72]Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee:
High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. J. Low Power Electron. 1(3): 259-272 (2005) - [j71]Sanghamitra Roy, Prith Banerjee:
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. IEEE Trans. Computers 54(7): 886-896 (2005) - [c188]Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee:
Automatic extraction of function bodies from software binaries. ASP-DAC 2005: 928-931 - [c187]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium 2005: 28-33 - [c186]Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207 - [c185]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code. LCPC 2005: 76-90 - [c184]Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee:
Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. VLSI Design 2005: 267-273 - 2004
- [j70]Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 312-324 (2004) - [c183]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
Automatic translation of software binaries onto FPGAs. DAC 2004: 389-394 - [c182]Sanghamitra Roy, Prithviraj Banerjee:
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. DAC 2004: 484-487 - [c181]Nikolaos D. Liveris, Prithviraj Banerjee:
Power Aware Interface Synthesis for Bus-Based SoC Design. DATE 2004: 864-869 - [c180]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. FCCM 2004: 37-46 - [c179]Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
High level area, delay and power estimation for FPGAs. FPGA 2004: 249 - [c178]Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee:
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256 - [c177]Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
Macro-models for high level area and power estimation on FPGAs. ACM Great Lakes Symposium on VLSI 2004: 162-165 - [c176]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. ACM Great Lakes Symposium on VLSI 2004: 397-400 - [c175]Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee:
Handling Data Streams while Compiling C Programs onto Hardware. ISVLSI 2004: 271-272 - 2003
- [j69]Amitabh Mishra, Prithviraj Banerjee:
An Algorithm-Based Error Detection Scheme for the Multigrid Method. IEEE Trans. Computers 52(9): 1089-1099 (2003) - [j68]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
Reducing False Sharing and Improving Spatial Locality in a Unified Compilation Framework. IEEE Trans. Parallel Distributed Syst. 14(4): 337-354 (2003) - [c174]Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott:
Adaptive computing: what can it do, where can it go? ASP-DAC 2003: 463 - [c173]Prith Banerjee:
An overview of a compiler for mapping MATLAB programs onto FPGAs. ASP-DAC 2003: 477-482 - [c172]Pramod G. Joisha, Prithviraj Banerjee:
The MAGICA Type Inference Engine for MATLAB. CC 2003: 121-125 - [c171]Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe:
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. FCCM 2003: 263-264 - [c170]Alex K. Jones, Prithviraj Banerjee:
An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. FCCM 2003: 284-285 - [c169]Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson:
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. FPGA 2003: 237 - [c168]Alex K. Jones, Prithviraj Banerjee:
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. FPGA 2003: 244 - [c167]Pramod G. Joisha, Prithviraj Banerjee:
Static array storage optimization in MATLAB. PLDI 2003: 258-268 - 2002
- [j67]Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Automatic Parallelization of Compiled Event Driven VHDL Simulation. IEEE Trans. Computers 51(4): 380-394 (2002) - [c166]Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee:
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. CASES 2002: 188-197 - [c165]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Accurate Area and Delay Estimators for FPGAs. DATE 2002: 862-869 - [c164]Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi:
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. IWDC 2002: 246-256 - 2001
- [j66]Dhruva R. Chakrabarti, Prithviraj Banerjee:
Static Single Assignment Form for Message-Passing Programs. Int. J. Parallel Program. 29(2): 139-184 (2001) - [j65]Yanhong Yuan, Prithviraj Banerjee:
A Parallel Implementation of a Fast Multipole-Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers. J. Parallel Distributed Comput. 61(12): 1751-1774 (2001) - [j64]Pramod G. Joisha, Abhay Kanhere, Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary:
Handling context-sensitive syntactic issues in the design of a front-end for a MATLAB compiler. ACM SIGAPL APL Quote Quad 31(3): 27-40 (2001) - [j63]Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee:
A Layout-Conscious Iteration Space Transformation Technique. IEEE Trans. Computers 50(12): 1321-1336 (2001) - [j62]U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 207-225 (2001) - [j61]Pramod G. Joisha, Prithviraj Banerjee:
The Efficient Computation of Ownership Sets in HPF. IEEE Trans. Parallel Distributed Syst. 12(8): 769-788 (2001) - [j60]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé:
Static and Dynamic Locality Optimizations Using Integer Linear Programming. IEEE Trans. Parallel Distributed Syst. 12(9): 922-941 (2001) - [j59]Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh:
Power Optimization of Delay Constrained Circuits. VLSI Design 12(2): 125-138 (2001) - [c163]Pramod G. Joisha, Prithviraj Banerjee:
Correctly detecting intrinsic type errors in typeless languages such as MATLAB. APL 2001: 7-21 - [c162]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. ASP-DAC 2001: 645-648 - [c161]Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee:
Compiler Optimization of Dynamic Data Distributions for Distributed-Memory Multicomputers. Compiler Optimizations for Scalable Parallel Systems Languages 2001: 445-484 - [c160]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. DATE 2001: 722-728 - [c159]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prith Banerjee:
Parallelization of MATLAB Applications for a Multi-FPGA System. FCCM 2001: 1-9 - [c158]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
A System for Synthesizing Optimized FPGA Hardware from MATLAB. ICCAD 2001: 314-319 - [c157]Dhruva R. Chakrabarti, Prithviraj Banerjee:
Global optimization techniques for automatic parallelization of hybrid applications. ICS 2001: 166-180 - [c156]Pramod G. Joisha, U. Nagaraj Shenoy, Prithviraj Banerjee:
Computing Array Shapes in MATLAB. LCPC 2001: 395-410 - [c155]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, U. Nagaraj Shenoy:
Fpga Hardware Synthesis From Matlab. VLSI Design 2001: 299-304 - [c154]U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir:
Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. VLSI Design 2001: 305-310 - 2000
- [j58]Antonio Lain, Dhruva R. Chakrabarti, Prithviraj Banerjee:
Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications. IEEE Trans. Parallel Distributed Syst. 11(2): 119-135 (2000) - [j57]Mahmut T. Kandemir, Alok N. Choudhary, Prithviraj Banerjee, J. Ramanujam, U. Nagaraj Shenoy:
Minimizing Data and Synchronization Costs in One-Way Communication. IEEE Trans. Parallel Distributed Syst. 11(12): 1232-1251 (2000) - [c153]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. CASES 2000: 85-93 - [c152]U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary:
A System-Level Synthesis Algorithm with Guaranteed Solution Quality. DATE 2000: 417-424 - [c151]Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky:
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. FCCM 2000: 39-48 - [c150]Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee:
A C compiler for a processor with a reconfigurable functional unit. FPGA 2000: 95-100 - [c149]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Parallel algorithms for FPGA placement. ACM Great Lakes Symposium on VLSI 2000: 86-94 - [c148]Yanhong Yuan, Prithviraj Banerjee:
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. ICCD 2000: 133-138 - [c147]Malay Haldar, Anshuman Nayak, Abhay Kanhere, Pramod G. Joisha, U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
Match Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel. ICPP 2000: 145-152 - [c146]Victor Kim, Prithviraj Banerjee, Kaushik De:
Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations. ICPP 2000: 421-430 - [c145]Yanhong Yuan, Prithviraj Banerjee:
A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. IPDPS 2000: 323-330 - [c144]Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee:
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. ISCA 2000: 225-235 - [c143]Pramod G. Joisha, Prithviraj Banerjee:
Exploiting Ownership Sets in HPF. LCPC 2000: 259-273 - [e3]Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy:
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000. ACM 2000, ISBN 1-58113-251-4 [contents]
1990 – 1999
- 1999
- [j56]John A. Chandy, Prithviraj Banerjee:
A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement. J. Parallel Distributed Comput. 57(1): 64-90 (1999) - [j55]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
A Matrix-Based Approach to Global Locality Optimization. J. Parallel Distributed Comput. 58(2): 190-235 (1999) - [j54]Pradeep Prabhakaran, Prithviraj Banerjee:
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. IEEE Trans. Computers 48(7): 762-768 (1999) - [j53]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, U. Nagaraj Shenoy:
A global communication optimization technique based on data-flow analysis and linear algebra. ACM Trans. Program. Lang. Syst. 21(6): 1251-1297 (1999) - [j52]Mahmut T. Kandemir, Alok N. Choudhary, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam:
A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts. IEEE Trans. Parallel Distributed Syst. 10(2): 115-135 (1999) - [j51]Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh:
Placement with Incomplete Data. VLSI Design 10(1): 57-70 (1999) - [c142]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors. IEEE PACT 1999: 203-211 - [c141]Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee:
An Approxmimate Algorithm for Delay-Constraint Technology Mapping. DAC 1999: 367-372 - [c140]Amitabh Mishra, Prithviraj Banerjee:
An Algorithm Based Error Detection Scheme for the Multigrid Algorithm. FTCS 1999: 12-19 - [c139]Yanhong Yuan, Prithviraj Banerjee:
ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. Great Lakes Symposium on VLSI 1999: 64-67 - [c138]Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran:
An Incremental Floorplanner. Great Lakes Symposium on VLSI 1999: 248-251 - [c137]Yanhong Yuan, Prithviraj Banerjee:
A Parallel 3-D Capacitance Extraction Program. HiPC 1999: 202-206 - [c136]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
A Framework for Interprocedural Locality Optimization Using Both Loop and Data Layout Transformations. ICPP 1999: 95-102 - [c135]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé:
An integer linear programming approach for optimizing cache locality. International Conference on Supercomputing 1999: 500-509 - [c134]Dhruva R. Chakrabarti, Prithviraj Banerjee:
A Novel Compilation Framework for Supporting Semi-Regular Distributions in Hybrid Applications. IPPS/SPDP 1999: 597-602 - [c133]Pramod G. Joisha, Prithviraj Banerjee:
PARADIGM (version 2.0): A New HPF Compilation System. IPPS/SPDP 1999: 609-615 - [c132]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality. IPPS/SPDP 1999: 738-743 - [c131]Jer-Sheng Chen, Prithviraj Banerjee:
Parallel construction algorithms for BDDs. ISCAS (1) 1999: 318-322 - [c130]Yanhong Yuan, Prithviraj Banerjee:
Incremental capacitance extraction and its application to iterative timing-driven detailed routing. ISPD 1999: 42-47 - [c129]Dhruva R. Chakrabarti, Prithviraj Banerjee:
Accurate Data and Context Management in Message-Passing Programs. LCPC 1999: 117-132 - [c128]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
Improving Locality Using a Graph-Based Technique for Detecting Memory Layouts of Arrays. PP 1999 - [c127]Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh:
Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. VLSI Design 1999: 423-427 - [e2]Prithviraj Banerjee, Viktor K. Prasanna, Bhabani P. Sinha:
High Performance Computing - HiPC'99, 6th International Conference, Calcutta, India, December 17-20, 1999, Proceedings. Lecture Notes in Computer Science 1745, Springer 1999, ISBN 3-540-66907-8 [contents] - 1998
- [j50]Gagan Hasteer, Prithviraj Banerjee:
A Parallel Algorithm for State Assignment of Finite State Machines. IEEE Trans. Computers 47(2): 242-246 (1998) - [j49]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. ACM Trans. Design Autom. Electr. Syst. 3(4): 600-625 (1998) - [c126]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
A Matrix-Based Approach to the Global Locality Optimization Problem. IEEE PACT 1998: 306-313 - [c125]Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh:
Potential-NRG: Placement with Incomplete Data. DAC 1998: 279-282 - [c124]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. DAC 1998: 611-614 - [c123]Victor Kim, Prithviraj Banerjee:
Parallel Algorithms for Power Estimation. DAC 1998: 672-677 - [c122]Sumit Roy, Harm Arts, Prithviraj Banerjee:
PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions. DATE 1998: 967-968 - [c121]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, U. Nagaraj Shenoy, Prithviraj Banerjee:
Enhancing Spatial Locality via Data Layout Optimizations. Euro-Par 1998: 422-434 - [c120]Dhruva R. Chakrabarti, Pramod G. Joisha, John A. Chandy, Krishnaswamy Krishnaswamy, Venkatram Krishnaswamy, Prithviraj Banerjee:
WADE: a Web-based automated parallel CAD environment. HiPC 1998: 473-480 - [c119]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using retiming. ICCAD 1998: 557-562 - [c118]Sumit Roy, Harm Arts, Prithviraj Banerjee:
PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis. ICCAD 1998: 601-606 - [c117]Sumit Roy, Harm Arts, Prithviraj Banerjee:
A low-power logic optimization methodology based on a fast power-driven mapping. ICCD 1998: 175-181 - [c116]Zhaoyun Xing, Prithviraj Banerjee:
A Parallel Algorithm for Timing-driven Global Routing for Standard Cells. ICPP 1998: 54-61 - [c115]Mahmut T. Kandemir, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam, Alok N. Choudhary:
Minimizing Data and Synchronization Costs in One-Way Communication. ICPP 1998: 180-188 - [c114]Dhruva R. Chakrabarti, U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
An Efficient Uniform Run-time Scheme for Mixed Regular-irregular Applications. International Conference on Supercomputing 1998: 61-68 - [c113]Mahmut T. Kandemir, Alok N. Choudhary, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam:
A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests. International Conference on Supercomputing 1998: 69-76 - [c112]Venkatram Krishnaswamy, Prithviraj Banerjee:
Parallel Compiled Event Driven VHDL Simulation. International Conference on Supercomputing 1998: 297-304 - [c111]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, U. Nagaraj Shenoy:
A Generalized Framework for Global Communication Optimization. IPPS/SPDP 1998: 69-73 - [c110]Dhruva R. Chakrabarti, Prithviraj Banerjee, Antonio Lain:
Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications. IPPS/SPDP 1998: 74-79 - [c109]Zhaoyun Xing, Prithviraj Banerjee:
A parallel algorithm for zero skew clock tree routing. ISPD 1998: 118-123 - [c108]Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee:
A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality. LCPC 1998: 34-50 - [c107]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
Improving Locality Using Loop and Data Transformations in an Integrated Framework. MICRO 1998: 285-297 - [c106]Sumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh:
Partitioning sequential circuits for low power. VLSI Design 1998: 212-217 - [c105]Pradeep Prabhakaran, Prithviraj Banerjee:
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. VLSI Design 1998: 428-434 - 1997
- [j48]Gagan Hasteer, Prithviraj Banerjee:
Simulated Annealing Based Parallel State Assignment of Finite State Machines. J. Parallel Distributed Comput. 43(1): 21-35 (1997) - [j47]Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
Implications of VHDL timing models on simulation and software synthesis. J. Syst. Archit. 44(1): 23-36 (1997) - [j46]John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee:
An evaluation of parallel simulated annealing strategies with application to standard cell placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4): 398-410 (1997) - [j45]Balkrishna Ramkumar, Prithviraj Banerjee:
ProperTEST: a portable parallel test generator for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 555-569 (1997) - [j44]Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee:
A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. IEEE Trans. Parallel Distributed Syst. 8(11): 1098-1116 (1997) - [c104]Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
A procedure for software synthesis from VHDL models. ASP-DAC 1997: 593-598 - [c103]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Efficient Assertion Checker for Combinational Properties. DAC 1997: 734-739 - [c102]John G. Holm, Steven Parkes, Prithviraj Banerjee:
Performance Evaluation of a C++ Library Based Multithreaded System. HICSS (1) 1997: 282-291 - [c101]John A. Chandy, Prithviraj Banerjee:
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. ICCD 1997: 621-627 - [c100]Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Load Balancing and Workload Minimization Of Overlapping Parallel Tasks. ICPP 1997: 272-279 - [c99]Dilip Krishnaswamy, Prithviraj Banerjee:
Exploiting task and data parallelism in parallel Hough and Radon transforms. ICPP 1997: 441-445 - [c98]John G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. International Conference on Supercomputing 1997: 172-179 - [c97]Zhaoyun Xing, John A. Chandy, Prithviraj Banerjee:
Parallel Global Routing Algorithms for Standard Cells. IPPS 1997: 527- - [c96]Sumit Roy, Prithviraj Banerjee:
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. IPPS 1997: 665-671 - [c95]Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel:
Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation 1997: 30-37 - [c94]Gagan Hasteer, Prithviraj Banerjee:
Simulated Annealing Based Parallel State Assignment of Finite State Machines. VLSI Design 1997: 69-75 - [c93]Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481 - [c92]Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS 1997: 274-281 - 1996
- [j43]Ky MacPherson, Prithviraj Banerjee:
Parallel Algorithms for VLSI Layout Verification. J. Parallel Distributed Comput. 36(2): 156-172 (1996) - [j42]Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee:
Dynamic Data Partitioning for Distributed-Memory Multicomputers. J. Parallel Distributed Comput. 38(2): 158-175 (1996) - [j41]Shankar Ramaswamy, Barbara Simons, Prithviraj Banerjee:
Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers. J. Parallel Distributed Comput. 38(2): 217-228 (1996) - [j40]Amber Roy-Chowdhury, Prithviraj Banerjee:
A New Error Analysis Based Method for Tolerance Computation for Algorithm-Based Checks. IEEE Trans. Computers 45(2): 238-243 (1996) - [j39]Amber Roy-Chowdhury, Nikolaos Bellas, Prithviraj Banerjee:
Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations. IEEE Trans. Computers 45(4): 394-407 (1996) - [j38]V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee:
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. IEEE Trans. Computers 45(4): 499-503 (1996) - [j37]Amber Roy-Chowdhury, Prithviraj Banerjee:
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems. IEEE Trans. Computers 45(11): 1239-1247 (1996) - [c91]Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831 - [c90]Amber Roy-Chowdhury, Prithviraj Banerjee:
Compiler-Assisted Generation of Error-Detecting Parallel Programs. FTCS 1996: 360-369 - [c89]Pradeep Prabhakaran, Prithviraj Banerjee:
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. ICCD 1996: 66-71 - [c88]Daniel J. Palermo, Ernesto Su, Eugene W. Hodges IV, Prithviraj Banerjee:
Compiler Support for Privatization on Distributed-Memory Machines. ICPP, Vol. 3 1996: 17-24 - [c87]Gagan Hasteer, Prithviraj Banerjee:
A Parallel Algorithm for State Assignment of Finite State Machines. ICPP, Vol. 2 1996: 37-45 - [c86]Antonio Lain, Prithviraj Banerjee:
Compiler Support for Hybrid Irregular Accesses on Multicomputers. International Conference on Supercomputing 1996: 1-9 - [c85]Shankar Ramaswamy, Eugene W. Hodges IV, Prithviraj Banerjee:
Compiling MATLAB Programs to ScaLAPACK: Exploiting Task and Data Parallelism. IPPS 1996: 613-619 - [c84]John A. Chandy, Steven Parkes, Prithviraj Banerjee:
Distributed Object Oriented Data Structures and Algorithms for VLSI CAD. IRREGULAR 1996: 147-158 - [c83]Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee:
Interprocedural Array Redistribution Data-Flow Analysis. LCPC 1996: 435-449 - [c82]Venkatram Krishnaswamy, Prithviraj Banerjee:
Actor Based Parallel VHDL Simulation Using Time Warp. Workshop on Parallel and Distributed Simulation 1996: 135-142 - [c81]Ky McPherson, Prithviraj Banerjee:
Integrating task and data parallelism in an irregular application: a case study. SPDP 1996: 208-213 - [c80]John A. Chandy, Prithviraj Banerjee:
Parallel simulated annealing strategies for VLSI cell placement. VLSI Design 1996: 37-42 - 1995
- [j36]Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, Ernesto Su:
The Paradigm Compiler for Distributed-Memory Multicomputers. Computer 28(10): 37-47 (1995) - [j35]Shankar Ramaswamy, Prithviraj Banerjee:
Simultaneous Allocation and Scheduling Using Convex Programming Techniques. Parallel Process. Lett. 5: 587-598 (1995) - [j34]Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel:
Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 333-338 (1995) - [c79]Michael Peercy, Prithviraj Banerjee:
Software Schemes of Reconfiguration and Recovery in Distributed Memory Multicomputers Using the Actor Model. FTCS 1995: 479-488 - [c78]Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
A parallel algorithm for fault simulation based on PROOFS . ICCD 1995: 616-621 - [c77]Ernesto Su, Antonio Lain, Shankar Ramaswamy, Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee:
Advanced Compilation Techniques in the PARADIGM Compiler for Distributed-memory Multicomputers. International Conference on Supercomputing 1995: 424-433 - [c76]Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee:
Parallel algorithms for logic synthesis using the MIS approach. IPPS 1995: 579-585 - [c75]Antonio Lain, Prithviraj Banerjee:
Exploiting spatial regularity in irregular iterative applications. IPPS 1995: 820-826 - [c74]Daniel J. Palermo, Prithviraj Banerjee:
Automatic Selection of Dynamic Data Partitioning Schemes for Distributed-Memory Multicomputers. LCPC 1995: 392-406 - [e1]Prithviraj Banerjee:
Proceedings of the 1995 International Conference on Parallel Processing, Urbana-Champain, Illinois, USA, August 14-18, 1995. Volume I: Architecture. CRC Press 1995, ISBN 0-8493-2615-X [contents] - 1994
- [b2]Prithviraj Banerjee:
Parallel algorithms for VLSI computer-aided design. Prentice Hall 1994, ISBN 978-0-13-015835-2, pp. I-XX, 1-699 - [j33]Prithviraj Banerjee, Michael Peercy:
Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults. IEEE Trans. Computers 43(7): 841-848 (1994) - [j32]Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee:
A portable parallel algorithm for logic synthesis using transduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 566-580 (1994) - [j31]Balkrishna Ramkumar, Prithviraj Banerjee:
ProperCAD: A portable object-oriented parallel environment for VLSI CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 829-842 (1994) - [j30]Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee:
RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 186-195 (1994) - [c73]Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. DAC 1994: 717-721 - [c72]Amber Roy-Chowdhury, Prithviraj Banerjee:
Algorithm-Based Fault Location and Recovery for Matrix Computations. FTCS 1994: 38-47 - [c71]Daniel J. Palermo, Ernesto Su, John A. Chandy, Prithviraj Banerjee:
Communication Optimizations Used in the PARADIGM Compiler for Distributed Memory Multicomputers. ICPP (2) 1994: 1-10 - [c70]Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee:
A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. ICPP (2) 1994: 116-125 - [c69]Kaushik De, Prithviraj Banerjee:
Parallel Logic Synthesis Using Partitioning. ICPP (3) 1994: 135-142 - [c68]Antonio Lain, Prithviraj Banerjee:
Techniques to overlap computation and communication in irregular iterative applications. International Conference on Supercomputing 1994: 236-245 - [c67]Ernesto Su, Daniel J. Palermo, Prithviraj Banerjee:
Processor Tagged Descriptors: A Data Structure for Compiling for Distributed-Memory Multicomputers. IFIP PACT 1994: 123-132 - [c66]Sungho Kim, Prithviraj Banerjee, Balkrishna Ramkumar, Steven Parkes, John A. Chandy:
ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement. IPPS 1994: 932-941 - [c65]Steven Parkes, John A. Chandy, Prithviraj Banerjee:
A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application. SC 1994: 69-78 - 1993
- [j29]A. L. Narasimha Reddy, John A. Chandy, Prithviraj Banerjee:
Design and Evaluation of Gracefully Degradable Disk Arrays. J. Parallel Distributed Comput. 17(1-2): 28-40 (1993) - [j28]Michael Peercy, Prithviraj Banerjee:
Fault tolerant VLSI systems. Proc. IEEE 81(5): 745-758 (1993) - [j27]Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee:
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 557-567 (1993) - [j26]Kaushik De, Prithviraj Banerjee:
PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 514-525 (1993) - [c64]Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel:
Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241 - [c63]Amber Roy-Chowdhury, Prithviraj Banerjee:
Tolerance Determination for Algorithm-Based Checks Using Simplified Error Analysis Techniques. FTCS 1993: 290-298 - [c62]Ernesto Su, Daniel J. Palermo, Prithviraj Banerjee:
Automating Parallelization of Regular Computations for Distributed-Memory. ICPP (2) 1993: 30-38 - [c61]Amber Roy-Chowdhury, Prithviraj Banerjee:
A Fault-Tolerant Parallel Algorithm for Iterative Solution of the Laplace Equation. ICPP (3) 1993: 133-140 - [c60]Shankar Ramaswamy, Prithviraj Banerjee:
Processor Allocation and Scheduling of Macro Dataflow Graphs on Distributed Memory Multicomputers by the PARADIGM Compiler. ICPP (2) 1993: 134-138 - [c59]John A. Chandy, Prithviraj Banerjee:
Reliability Evalutaion of Disk Array Architectures. ICPP (1) 1993: 263-267 - [c58]Manish Gupta, Prithviraj Banerjee:
PARADIGM: A Compiler for Automatic Data Distribution on Multicomputers. International Conference on Supercomputing 1993: 87-96 - [c57]Balkrishna Ramkumar, Prithviraj Banerjee:
A Portable Parallel Algorithm for VLSI Circuit Extraction. IPPS 1993: 434-438 - [c56]Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga:
A Shared Memory Parallel Algorithm for Logic Synthesis. VLSI Design 1993: 317-322 - [p1]Prithviraj Banerjee:
A Survey of Parallel Algorithms for VLSI cell Placement. Algorithmic Aspects of VLSI Layout 1993: 69-131 - 1992
- [j25]Krishna P. Belkhale, Prithviraj Banerjee:
Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach. IEEE Trans. Computers 41(1): 83-96 (1992) - [j24]Krishna P. Belkhale, Prithviraj Banerjee:
Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor. IEEE Trans. Computers 41(6): 699-709 (1992) - [j23]Manish Gupta, Prithviraj Banerjee:
Demonstration of Automatic Data Partitioning Techniques for Parallelizing Compilers on Multicomputers. IEEE Trans. Parallel Distributed Syst. 3(2): 179-193 (1992) - [j22]Jiun-Ming Hsu, Prithviraj Banerjee:
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. IEEE Trans. Parallel Distributed Syst. 3(4): 451-464 (1992) - [c55]Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel:
APT: An Area-Performance-Testability Driven Placement Algorithm. DAC 1992: 141-146 - [c54]Michael Peercy, Prithviraj Banerjee:
Design and Analysis of Software Reconfiguration Strategies for Hypercube Multicomputers under Multiple Faults. FTCS 1992: 448-455 - [c53]Balkrishna Ramkumar, Prithviraj Banerjee:
Portable parallel test generation for sequential circuits. ICCAD 1992: 220-223 - [c52]Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee:
ProperSYN: a portable parallel algorithm for logic synthesis. ICCAD 1992: 412-416 - [c51]Balkrishna Ramkumar, Prithviraj Banerjee:
ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD. ICCD 1992: 544-548 - [c50]John G. Holm, Prithviraj Banerjee:
Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions. ICPP (1) 1992: 192-195 - [c49]Manish Gupta, Prithviraj Banerjee:
A methodology for high-level synthesis of communication on multicomputers. ICS 1992: 357-367 - [c48]Manish Gupta, Prithviraj Banerjee:
Compile-Time Estimation of Communication Costs on Multicomputers. IPPS 1992: 470-475 - 1991
- [j21]Krishna P. Belkhale, Prithviraj Banerjee:
Parallel algorithms for VLSI circuit extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 604-618 (1991) - [j20]Ralph-Michael Kling, Prithviraj Banerjee:
Empirical and theoretical studies of the simulated evolution method applied to standard cell placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(10): 1303-1315 (1991) - [j19]Srinivas Patil, Prithviraj Banerjee:
Performance trade-offs in a parallel test generation/fault simulation environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1542-1558 (1991) - [c47]Srinivas Patil, Prithviraj Banerjee, Janak H. Patel:
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC 1991: 155-159 - [c46]David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
Functional abstraction of logic gates for switch-level simulation. EURO-DAC 1991: 329-333 - [c45]A. L. Narasimha Reddy, Prithviraj Banerjee:
Gracefully Degradable Disk Arrays. FTCS 1991: 401-409 - [c44]A. L. Narasimha Reddy, Prithviraj Banerjee, D. K. Chen:
Compiler Support for Parallel I/O Operations. ICPP (2) 1991: 290-291 - [c43]Vijay Balasubramanian, Prithviraj Banerjee:
CRAFT: Compiler-Assisted Algorithm-Based Fault Tolerance in Distributed Memory Multiprocessors. ICPP (1) 1991: 501-504 - [c42]Jiun-Ming Hsu, Prithviraj Banerjee:
Performance Evaluation of Hardware Support for Message Passing in Distributed Memory Multicomputers. ICPP (1) 1991: 604-607 - [c41]Krishna P. Belkhale, Prithviraj Banerjee:
A Scheduling Algorithm for Parallelizable Dependent Tasks. IPPS 1991: 500-506 - [c40]Sungho Kim, Prithviraj Banerjee, Srinivas Patil:
A Layout Driven Design for Testability Technique for MOS VLSI Circuits. ITC 1991: 157-165 - [c39]Kaushik De, Prithviraj Banerjee:
Logic Partitioning and Resynthesis for Testability. ITC 1991: 906-915 - 1990
- [j18]Vijay Balasubramanian, Prithviraj Banerjee:
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors. IEEE Trans. Computers 39(4): 436-446 (1990) - [j17]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham:
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990) - [j16]A. L. Narasimha Reddy, Prithviraj Banerjee:
Algorithms-Based Fault Detection for Signal Processing Applications. IEEE Trans. Computers 39(10): 1304-1308 (1990) - [j15]Srinivas Patil, Prithviraj Banerjee:
A parallel branch and bound algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 313-322 (1990) - [j14]Prithviraj Banerjee, Mark Howard Jones, Jeff S. Sargent:
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors. IEEE Trans. Parallel Distributed Syst. 1(1): 91-106 (1990) - [j13]A. L. Narasimha Reddy, Prithviraj Banerjee:
Design, Analysis, and Simulation of I/O Architectures for Hypercube. IEEE Trans. Parallel Distributed Syst. 1(2): 140-151 (1990) - [j12]Vijay Balasubramanian, Prithviraj Banerjee:
Tradeoffs in the Design of Efficient Algorithm-Based Error Detection Schemes for Hypercube Multiprocessors. IEEE Trans. Software Eng. 16(2): 183-196 (1990) - [c38]Ralph-Michael Kling, Prithviraj Banerjee:
Optimization by Simulated Evolution with Applications to Standard Cell Placement. DAC 1990: 20-25 - [c37]Randall J. Brouwer, Prithviraj Banerjee:
PHIGURE: A Parallel Hierarchical Global Router. DAC 1990: 650-653 - [c36]Prithviraj Banerjee:
Strategies for reconfiguring hypercubes under faults. FTCS 1990: 210-217 - [c35]Michael Peercy, Prithviraj Banerjee:
Distributed algorithms for shortest-path, deadlock-free routing and broadcasting in arbitrarily faulty hypercubes. FTCS 1990: 218-225 - [c34]David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69 - [c33]Krishna P. Belkhale, Prithviraj Banerjee:
A Parallel Algorithm for Hierarchical Circuit Extraction. ICCAD 1990: 236-239 - [c32]David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham:
Automatic classification of node types in switch-level descriptions. ICCD 1990: 175-178 - [c31]Krishna P. Belkhale, Prithviraj Banerjee:
An Approximate Algorithm for the Partitionable Independent Task Scheduling Problem. ICPP (1) 1990: 72-75 - [c30]Krishna P. Belkhale, Prithviraj Banerjee:
Geometric Connected Component Labeling on Distributed Memory Multicomputers. ICPP (3) 1990: 291-294 - [c29]Jiun-Ming Hsu, Prithviraj Banerjee:
Hardware Support for Message Routing in a Distributed Memory Multicomputer. ICPP (1) 1990: 508-515 - [c28]Jiun-Ming Hsu, Prithviraj Banerjee:
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. ISCA 1990: 260-269 - [c27]A. L. Narasimha Reddy, Prithviraj Banerjee:
A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor. ISCA 1990: 312-321 - [c26]Jiun-Ming Hsu, Prithviraj Banerjee:
A message passing coprocessor for distributed memory multicomputers. SC 1990: 720-729
1980 – 1989
- 1989
- [j11]A. L. Narasimha Reddy, Prithviraj Banerjee:
A study parallel disk organizations. SIGARCH Comput. Archit. News 17(5): 40-47 (1989) - [j10]Prithviraj Banerjee, Abhijeet Dugar:
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive. IEEE Trans. Computers 38(1): 30-46 (1989) - [j9]A. L. Narasimha Reddy, Prithviraj Banerjee:
An Evaluation of Multiple-Disk I/O Systems. IEEE Trans. Computers 38(12): 1680-1690 (1989) - [j8]Ralph-Michael Kling, Prithviraj Banerjee:
ESp: Placement by simulated evolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(3): 245-256 (1989) - [c25]Srinivas Patil, Prithviraj Banerjee:
A Parallel Branch and Bound Algorithm for Test Generation. DAC 1989: 339-343 - [c24]Jeff S. Sargent, Prithviraj Banerjee:
A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. DAC 1989: 590-593 - [c23]Sungho Kim, Prithviraj Banerjee:
An accurate timing model for fault simulation in MOS circuits. ICCAD 1989: 76-79 - [c22]Krishna P. Belkhale, Prithviraj Banerjee:
PACE2: an improved parallel VLSI extractor with parameter extraction. ICCAD 1989: 526-529 - [c21]Robert B. Mueller-Thuns, David McFarland, Prithviraj Banerjee:
Algorithm-Based Fault Tolerance for Adaptive Least Squares Lattice Filtering on a Hypercube Multiprocessor. ICPP (3) 1989: 177-180 - [c20]A. L. Narasimha Reddy, Prithviraj Banerjee:
Performance Evaluation of Multiple-Disk I/O Systems. ICPP (1) 1989: 315-318 - [c19]A. L. Narasimha Reddy, Prithviraj Banerjee:
I/O issues for hypercubes. ICS 1989: 72-81 - [c18]Srinivas Patil, Prithviraj Banerjee:
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. ITC 1989: 718-726 - [c17]Vijay Balasubramanian, Prithviraj Banerjee:
Algorithm-based Error Detection for Signal Processing Applications on a Hypercube Multiprocessor. RTSS 1989: 134-143 - [c16]Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos:
Efficient circuit partitioning algorithms for parallel logic simulation. SC 1989: 361-370 - 1988
- [j7]Prithviraj Banerjee:
The Cubical Ring Connected Cycles: A Fault-Tolerant Parallel Computation Network. IEEE Trans. Computers 37(5): 632-636 (1988) - [j6]Douglas B. West, Prithviraj Banerjee:
On the Construction of Communication Networks Satisfying Bounded Fan-In of Service Ports. IEEE Trans. Computers 37(9): 1148-1151 (1988) - [c15]Prithviraj Banerjee, Craig B. Stunkel:
A novel approach to system-level fault tolerance in hypercube multiprocessors. C³P 1988: 307-311 - [c14]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham:
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS 1988: 362-367 - [c13]Krishna P. Belkhale, Prithviraj Banerjee:
PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor. ICCAD 1988: 326-329 - [c12]Randall J. Brouwer, Prithviraj Banerjee:
A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor. ICCD 1988: 4-7 - [c11]Krishna P. Belkhale, Prith Banerjee:
Reconfiguration strategies in VLSI processor arrays. ICCD 1988: 418-421 - [c10]A. L. Narasimha Reddy, Prithviraj Banerjee:
I/O Embedding in Hypercubes. ICPP (1) 1988: 331-338 - 1987
- [j5]Jacob A. Abraham, Prithviraj Banerjee, Chien-Yi Chen, W. Kent Fuchs, Sy-Yen Kuo, A. L. Narasimha Reddy:
Fault Tolerance Techniques for Systolic Arrays. Computer 20(7): 65-75 (1987) - [j4]Vijay Balasubramanian, Prithviraj Banerjee:
A Fault Tolerant Massively Parallel Processing Architecture. J. Parallel Distributed Comput. 4(4): 363-383 (1987) - [c9]Ralph-Michael Kling, Prithviraj Banerjee:
ESP: A New Standard Cell Placement Package Using Simulated Evolution. DAC 1987: 60-66 - [c8]Mark Jones, Prithviraj Banerjee:
Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube. DAC 1987: 807-813 - [c7]A. L. Narasimha Reddy, Prithviraj Banerjee:
A Fault Secure Dictionary Machine. ICDE 1987: 104-110 - [c6]Vijay Balasubramanian, Prithviraj Banerjee:
A Fixed Size Array Processor for Computing the Fast Fourier Transform. RTSS 1987: 36-43 - 1986
- [j3]Prithviraj Banerjee, Jacob A. Abraham:
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. IEEE Trans. Computers 35(4): 296-306 (1986) - [c5]Prithviraj Banerjee, Abhijeet Dugar:
A Fault-Tolerant Interconnection Network Supporting the Fetch-And-Add Primitive. ICPP 1986: 327-334 - [c4]Vijay Balasubramanian, Prithviraj Banerjee:
RECBAR : A Reconfigurable Massively Parallel Processing Architecture. ICPP 1986: 390-393 - [c3]Prithviraj Banerjee, Jacob A. Abraham:
A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems. RTSS 1986: 72-78 - 1985
- [b1]Prithviraj Banerjee:
A Theory for Algorithm-Based Fault Tolerance in Array Processor Systems. University of Illinois Urbana-Champaign, USA, 1985 - [j2]Prithviraj Banerjee, Jacob A. Abraham:
A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 312-321 (1985) - 1984
- [j1]Prithviraj Banerjee, Jacob A. Abraham:
Characterization and Testing of Physical Failures in MOS Logic Circuits. IEEE Des. Test 1(3): 76-86 (1984) - [c2]Prithviraj Banerjee, Jacob A. Abraham:
Fault-Secure Algorithms for Multiple-Processor Systems. ISCA 1984: 279-287 - 1983
- [c1]Prithviraj Banerjee, Jacob A. Abraham:
Generating Tests for Physical Failures in MOS Logic Circuits. ITC 1983: 554-559
Coauthor Index
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