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ORCID35th DFT 2020: Frascati, Italy
- Luigi Dilillo, Mihalis Psarakis, Taniya Siddiqua:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, Frascati, Italy, October 19-21, 2020. IEEE 2020, ISBN 978-1-7281-9457-8 - Hussein Bazzi, Jérémy Postel-Pellerin, Hassen Aziza, Mathieu Moreau
, Adnan Harb:
Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation. 1-4 - Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella:
Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms. 1-4 - Xiaohan Yang, Saurabh Khandelwal, Aiqi Jiang, Abusaleh M. Jabir:
A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function. 1-4 - Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi:
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. 1-4 - Irith Pomeranz:
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults. 1-4 - Danilo Cappellone, Stefano Di Mascio, Gianluca Furano, Alessandra Menicucci, Marco Ottavi:
On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor. 1-6 - Avijit Chakraborty, D. M. H. Walker:
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. 1-4 - Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. 1-6 - Zhen Gao, Xiaohui Wei, Han Zhang, Wenshuo Li, Guangjun Ge, Yu Wang, Pedro Reviriego:
Reliability Evaluation of Pruned Neural Networks against Errors on Parameters. 1-6 - Giorgio Di Natale, Francesco Regazzoni, Vincent Albanese, Frank Lhermet, Yann Loisel, Abderrahmane Sensaoui, Samuel Pagliarini:
Latest Trends in Hardware Security and Privacy. 1-4 - Rubens Luiz Rech Junior, Paolo Rech:
Impact of Layers Selective Approximation on CNNs Reliability and Performance. 1-4 - Aein Rezaei Shahmirzadi, Amir Moradi:
Clock Glitch versus SIFA. 1-6 - Basma Hajri, Mohammad M. Mansour, Ali Chehab, Hassen Aziza:
A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications. 1-4 - Zhen Gao, Han Zhang, Xiaohui Wei, Tong Yan, Kangkang Guo, Wenshuo Li, Yu Wang, Pedro Reviriego:
Reliable Classification with Ensemble Convolutional Neural Networks. 1-4 - Nagabhushan Reddy, Sankaran Menon, Prashant D. Joshi:
Validation Challenges in Recent Trends of Power Management in Microprocessors. 1-6 - Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. 1-6 - Cristiana Bolchini, Luca Cassano, Antonio Miele, Matteo Biasielli:
Lightweight Fault Detection and Management for Image Restoration. 1-6 - Junchao Chen, Thomas Lange, Marko S. Andjelkovic, Aleksandar Simevski, Milos Krstic:
Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction. 1-6 - Dario Mamone, Alberto Bosio, Alessandro Savino, Said Hamdioui, Maurizio Rebaudengo:
On the Analysis of Real-time Operating System Reliability in Embedded Systems. 1-6 - Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo:
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. 1-6 - Annachiara Ruospo, Angelo Balaara, Alberto Bosio, Ernesto Sánchez:
A Pipelined Multi-Level Fault Injector for Deep Neural Networks. 1-6 - Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network. 1-4 - Athanasios Papadimitriou, Konstantinos Nomikos, Mihalis Psarakis, Ehsan Aerabi, David Hély:
You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers. 1-6 - Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri:
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. 1-6 - Corrado De Sio, Sarah Azimi, Luca Sterpone:
An Emulation Platform for Evaluating the Reliability of Deep Neural Networks. 1-4 - Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. 1-6 - Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos:
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). 1-4 - Glenn H. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Ruoyi Zhao, Israel Koren, Zahava Koren:
Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation. 1-4 - Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems. 1-6 - Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis:
Efficient LDPC Encoder Designs for Magnetic Recording Media. 1-6 - T. Vayssade, Florence Azaïs, Laurent Latorre, François Lefevre:
EVM measurement of RF ZigBee transceivers using standard digital ATE. 1-6 - Soultana Ellinidou, Gaurav Sharma, Olivier Markowitch, Guy Gogniat, Jean-Michel Dricot:
A novel Network-on-Chip security algorithm for tolerating Byzantine faults. 1-6 - Gianluca Furano, Antonis Tavoularis, Marco Rovatti:
AI in space: applications examples and challenges. 1-6 - Christos Georgakidis, Christos P. Sotiriou:
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL. 1-6 - Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand:
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. 1-6
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last updated on 2024-09-25 00:32 CEST by the dblp team
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