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ORCID40th DFT 2025: Barcelona, Spain
- IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2025, Barcelona, Spain, October 21-23, 2025. IEEE 2025, ISBN 979-8-3315-1489-1
- Aghiles Douadi, Elena-Ioana Vatajelu, Paolo Maistri, Jean-Max Dutertre, David Hély, Vincent Beroulle, Giorgio Di Natale:
Laser Fault Injection on RO-Based PUFs Implemented on FPGA. 1-6 - Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic:
Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications. 1-6 - Jad Al Halabi, Melis Cetinkaya, Endri Kaja, Mounika Vaddeboina, Wolfgang Ecker:
Optimizing Software Self-Test Pattern Generation for Specific Components. 1-4 - Jin-Fu Li, Chun-Lung Hsu, Yu-Guang Chen, Ting-Yi Wu, Wei-Hung Lin, Shih-Hsu Huang, Yung-Chi Chia, Yu-Chieh Chen:
Special Session: Effective Design, Modeling and Testing Techniques for Digital Computing-in Memories with MAC Function. 1-8 - Théo Bermond, Adrian Evans:
Analysis of Repair Structures for Chiplet Interfaces. 1-7 - Benjamin Glätzer, Alexander Benedict Behrens:
Improved Encoding and Decoding of Optimal $m$-Out-of-$n$ Codes. 1-4 - Chandan Kumar Jha, Sumit Kumar Jha, Ulf Schlichtmann, Rolf Drechsler:
Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory. 1-8 - Jinhua Zhu, Zhen Gao, Pedro Reviriego, Shanshan Liu, Fabrizio Lombardi:
Dependability Analysis and Assessment of Approximate Membership Query XOR Filters. 1-4 - Livia Manovi, Riccardo Gallon, Gianluca Furano, Riccardo Rovatti, Mauro Mangia, Alessandra Menicucci, Fabian Schiemenz:
Beyond the Black Box: Advancing Transparency, Explainability, and Trust in AI for Space. 1-8 - Nikolaos Andriotis, Alejandro Serrano-Cases, Sergi Alcaide, Francisco J. Cazorla, Jaume Abella:
Flexible Software-Only Diverse Redundancy on COTS GPUs for Safety-Related Kernels. 1-4 - Dominik Rudolf, Ardavan Elahi, Axel Jantsch, Dinesh Pamunuwa:
A Fault-Tolerant Voter Circuit in NEM Technology. 1-6 - Mohammad Hasan Ahmadilivani, Yuto Kobayashi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Does Fault Tolerance Safeguard DNNs Against Bitfiip Attacks? A Case Study. 1-4 - Frédéric Pétrot, César Fuguet:
On the Hardware Implementation of Lala's 64-bit SEcDED Codes. 1-4 - Youssef A. Ait Alama, Sampada Sakpal, Ke Wang, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri:
Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults. 1-6 - D. Ronga, Eric Faehn, Patrick Girard, Arnaud Virazel:
Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment. 1-6 - Mohammadreza Amel Solouki, Corrado De Sio, Maurizio Rebaudengo, Jacopo Sini:
Automatic Data Redundancy in Safety-Critical Applications Using Trait-Based Code Transformation. 1-4 - Roberto Martínez, Alessandro Palumbo, Pedro Reviriego, Rubén Salvador, David Larrabeiti:
LAD-IXoC: Loop-Based Attack Detection with Integrated Xor Filter and CMS. 1-6 - Mohammad Ershad Shaik, Abhishek Kumar Mishra, Nagarajan Kandasamy, Nur A. Touba:
A Multi-Modal Attention-Based Framework for Good Die in Bad Neighborhood Methodology. 1-6 - Tatsuya Aono, Toshinori Hosokawa, Masayoshi Yoshimura, Koji Yamazaki, Masayuki Arai:
PBO-Based Pattern Replacement for Compacting Diagnostic Patterns to Achieve Complete Diagnostic Resolution. 1-6 - Ivan Rodriguez-Ferrandez, Eric Rufart Blasco, Leonidas Kosmidis, Maris Tali, David Steenari:
Radiation Effects on NVIDIA Jetson SoCs: Insights from Heavy Ion Irradiation. 1-4 - Wenqi Zhang, Shanshan Liu, Yinghao Cheng, Zhen Gao, Pedro Reviriego, Fabrizio Lombardi:
Approximate Memory Protection Against Double-Adjacent Bit Errors with Low Redundancy SEC-DAEC Codes. 1-6 - Asier Gambra, Durba Chatterjee, Unai Rioja, Igor Armendariz, Lejla Batina:
A Neural Network-Based Classifier for Glitch Detection in Clock Traces. 1-6 - Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Luigi Dilillo, Anuj Pathania, George Floros:
Compact SER Models for Line-Source-Induced Charge Collection Using Model Order Reduction. 1-6 - Thiago H. Rausch, Wesley Grignani, Luigi Dilillo, Douglas R. Melo:
Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture. 1-4 - Vittorio Turco, L. Fezza, Annachiara Ruospo, E. Sanchez, Matteo Sonza Reorda:
APSS Metrics for Fault Detection: Area, Position, Symmetry, and Shape in Image Segmentation. 1-6 - Mohammad Reza Heidari Iman, Rolf Drechsler, Chandan Kumar Jha, Ali Azarpeyvand, Tara Ghasempouri, Sharjeel Imtiaz, Jaan Raik, Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli, Giorgio Di Natale:
Special Session Paper: Application of Functional Verification Techniques in Hardware Trust. 1-8 - Nikolaos Chatzivangelis, Nikolaos Zazatis, Wesley Grignani, Georgios Ioannis Paliaroutis, Douglas A. dos Santos, Carolina Imianosky, Maria Kastriotou, Carlo Cazzaniga, Frédéric Wrobel, Alessandro Veronesi, Christos P. Sotiriou, Marko S. Andjelkovic, Fabian Luis Vargas, Davide Bertozzi, Luigi Dilillo:
Special Session Paper: Simulation Methodologies and Experiments for Reliability Analysis of Devices in Radiation Harsh Environments. 1-8 - Basile Darne, Abrarul Karim, Paul-Antoine Matrangolo, Joachim Falk, Ian O'Connor, Cédric Marchand, Alberto Bosio, Jürgen Teich:
Special Session Paper: FeMFET-Based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. 1-8 - Huifang Jiao, Xiaojie Wang, Xiaomeng Qi, Hongliang Pu, Zhiliang Hu:
Soft Error Study on Advanced Process Node DRAMs at Component and System Level. 1-5 - Jorge Cano-Páez, Luis Entrena, Almudena Lindoso:
Reliability Assessment of AMD MicroBlaze-V TMR Architecture Using Fault Injection. 1-6 - Nicola Di Gruttola Giardino, Paolo Bernardi, Sabrina Corpino, Fabrizio Stesina:
HW/SW Co-Design of a Reliable Deep Space System Exploiting Application-Profiled RAM Scrubbing. 1-6 - Irith Pomeranz:
Functional Synchronization for Online Testing of Identical Logic Blocks. 1-6 - Brent De Blaere, Jens Vankeirsbilck, Jeroen Boydens:
Using RISC-V Extensions to Support Software-Implemented Hardware Fault Tolerance. 1-6
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