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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 22
Volume 22, Number 1, December 2016
- Hai Wang, Jian Ma, Sheldon X.-D. Tan, Chi Zhang, He Tang, Keheng Huang, Zhenghong Zhang:
Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors. 1:1-1:21 - Sudip Poddar
, Sarmishtha Ghoshal, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip. 2:1-2:29 - Robert Czerwinski, Dariusz Kania:
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. 3:1-3:25 - Shirshendu Das, Hemangee K. Kapoor:
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. 4:1-4:26 - Yu-Wei Wu, Yiyu Shi, Sudip Roy, Tsung-Yi Ho:
Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization. 5:1-5:24 - Kan Xiao, Domenic Forte, Yier Jin, Ramesh Karri, Swarup Bhunia, Mark M. Tehranipoor:
Hardware Trojans: Lessons Learned after One Decade of Research. 6:1-6:23 - Irith Pomeranz:
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests. 7:1-7:22 - Jinyong Lee, Ingoo Heo, Yongje Lee, Yunheung Paek:
Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor. 8:1-8:29 - Yu-Ming Chang, Pi-Cheng Hsiu, Yuan-Hao Chang, Chi-Hao Chen, Tei-Wei Kuo, Cheng-Yuan Michael Wang:
Improving PCM Endurance with a Constant-Cost Wear Leveling Design. 9:1-9:27 - Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young:
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. 10:1-10:26 - Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities. 11:1-11:26 - Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen:
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures. 12:1-12:25 - Hossein Mehri, Bijan Alizadeh:
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models. 13:1-13:17 - Ganesh Gingade, Wenyi Chen, Yung-Hsiang Lu, Jan P. Allebach, Hernan Ildefonso Gutierrez-Vazquez:
Hybrid Power Management for Office Equipment. 14:1-14:22 - Joost-Pieter Katoen, Hao Wu:
Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow. 15:1-15:27 - Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. 16:1-16:26 - Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi, Sreenivas Gangadhar:
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection. 17:1-17:21 - Yi Wang, Zhiwei Qin, Renhai Chen, Zili Shao, Laurence T. Yang:
An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems. 18:1-18:22 - Piyoosh Purushothaman Nair, Arnab Sarkar, N. M. Harsha, Megha Gandhi, P. P. Chakrabarti, Sujoy Ghose:
ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems. 19:1-19:25
Volume 22, Number 2, March 2017
- Phuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay:
Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test. 20:1-20:28 - Di Zhu, Siyu Yue, Massoud Pedram, Lizhong Chen:
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks. 21:1-21:21 - Mohammad Reza Azarbad, Bijan Alizadeh:
Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis. 22:1-22:22 - Qingling Zhao, Zaid Al-bayati, Zonghua Gu, Haibo Zeng:
Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models. 23:1-23:25 - Hazem Ismail Ali, Sander Stuijk, Benny Akesson, Luís Miguel Pinho:
Reducing the Complexity of Dataflow Graphs Using Slack-Based Merging. 24:1-24:22 - Philipp Mundhenk, Andrew Paverd, Artur Mrowca, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty:
Security in Automotive Networks: Lightweight Authentication and Authorization. 25:1-25:27 - XianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang:
On the Restore Time Variations of Future DRAM Memory. 26:1-26:24 - Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. 27:1-27:22 - Hang Su, Dakai Zhu, Scott Brandt:
An Elastic Mixed-Criticality Task Model and Early-Release EDF Scheduling Algorithms. 28:1-28:25 - Irith Pomeranz:
Computation of Seeds for LFSR-Based n-Detection Test Generation. 29:1-29:13 - Can Hankendi, Ayse Kivilcim Coskun:
Scale & Cap: Scaling-Aware Resource Management for Consolidated Multi-threaded Applications. 30:1-30:22 - Jerry Backer, David Hély, Ramesh Karri:
Secure and Flexible Trace-Based Debugging of Systems-on-Chip. 31:1-31:25 - Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor:
A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors. 32:1-32:28 - Rui Santos, Shyamsundar Venkataraman, Akash Kumar:
Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices. 33:1-33:26 - Andrea Enrici, Ludovic Apvrille, Renaud Pacalet:
A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems. 34:1-34:25
- Twan Basten, Orlando Moreira, Robert de Groote:
Special Section: Integrating Dataflow, Embedded Computing and Architecture. 35:1-35:2 - Junchul Choi, Soonhoi Ha:
Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks. 36:1-36:26 - Hanwoong Jung, Hyunok Oh, Soonhoi Ha:
Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay. 37:1-37:25 - Adnan Bouakaz, Pascal Fradet, Alain Girault:
A Survey of Parametric Dataflow Models of Computation. 38:1-38:25 - Adnan Bouakaz, Pascal Fradet, Alain Girault:
Symbolic Analyses of Dataflow Graphs. 39:1-39:25
Volume 22, Number 3, May 2017
- Jaehyun Park, Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Vinson Young, Junghee Lee, Jongman Kim:
HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs. 40:1-40:25 - Li Tang, Richard F. Barrett, Jeanine E. Cook, Xiaobo Sharon Hu:
PeaPaw: Performance and Energy-Aware Partitioning of Workload on Heterogeneous Platforms. 41:1-41:26 - Kun Yang, Domenic Forte, Mark M. Tehranipoor:
CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability, and Authentication in the IoT Supply Chain. 42:1-42:31 - Irith Pomeranz:
Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults. 43:1-43:17 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque:
Application-Specific Residential Microgrid Design Methodology. 44:1-44:21 - Jin-Tai Yan:
Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs. 45:1-45:25 - Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. 46:1-46:27 - Guoyong Shi, Hanbin Hu, Shuwen Deng:
Topological Approach to Automatic Symbolic Macromodel Generation for Analog Integrated Circuits. 47:1-47:25 - Miseon Han, Youngsun Han, Seon Wook Kim, Hokyoon Lee, Il Park:
Content-Aware Bit Shuffling for Maximizing PCM Endurance. 48:1-48:26 - Shamik Saha, Prabal Basu, Chidhambaranathan Rajamanikkam, Aatreyi Bal, Koushik Chakraborty, Sanghamitra Roy:
SSAGA: SMs Synthesized for Asymmetric GPGPU Applications. 49:1-49:20 - Tiantao Lu, Ankur Srivastava:
Low-Power Clock Tree Synthesis for 3D-ICs. 50:1-50:24 - Woojoo Lee, Kyuseung Han, Yanzhi Wang, Tiansong Cui, Shahin Nazarian, Massoud Pedram:
TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management. 51:1-51:25 - Yongje Lee, Jinyong Lee, Ingoo Heo, Dongil Hwang, Yunheung Paek:
Using CoreSight PTM to Integrate CRA Monitoring IPs in an ARM-Based SoC. 52:1-52:25 - Yuankun Xue, Ji Li, Shahin Nazarian, Paul Bogdan:
Fundamental Challenges Toward Making the IoT a Reachable Reality: A Model-Centric Investigation. 53:1-53:25 - Zimu Guo, Jia Di, Mark M. Tehranipoor, Domenic Forte:
Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering. 54:1-54:31 - Mohammad Torabi, Lihong Zhang:
A Fast Hierarchical Adaptive Analog Routing Algorithm Based on Integer Linear Programming. 55:1-55:23 - Yang Song, Kambiz Samadi, Bill Lin:
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs. 56:1-56:23 - Ji Li, Jeffrey Draper:
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits. 57:1-57:21
Volume 22, Number 4, July 2017
- Kaige Yan, Lu Peng, Mingsong Chen, Xin Fu:
Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms. 58:1-58:20 - Taehyun Kim, Jongbum Lim, Jinku Kim, Woo-Cheol Cho, Eui-Young Chung, Hyuk-Jun Lee:
Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors. 59:1-59:26 - Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath:
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. 60:1-60:30 - Tobias Isenberg, Marco Platzner, Heike Wehrheim, Tobias Wiersema:
Proof-Carrying Hardware via Inductive Invariants. 61:1-61:23 - Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg:
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. 62:1-62:20 - Katherine Shu-Min Li, Sying-Jyan Wang:
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. 63:1-63:20 - Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino:
Approximate Energy-Efficient Encoding for Serial Interfaces. 64:1-64:25 - Benjamin Carrión Schäfer:
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies. 65:1-65:20 - Zahi Moudallal, Farid N. Najm:
Generating Current Constraints to Guarantee RLC Power Grid Safety. 66:1-66:39 - Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Test Modification for Reduced Volumes of Fail Data. 67:1-67:17 - Ya Wang, Di Gao, Dani A. Tannir, Ning Dong, G. Peter Fang, Wei Dong, Peng Li:
Multiharmonic Small-Signal Modeling of Low-Power PWM DC-DC Converters. 68:1-68:16 - Hassan Albalawi, Yuanning Li, Xin Li:
Training Fixed-Point Classifiers for On-Chip Low-Power Implementation. 69:1-69:18 - Mohaddeseh Hoveida, Fatemeh Aghaaliakbari, Ramin Bashizade, Mohammad Arjomand, Hamid Sarbazi-Azad:
Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era. 70:1-70:26 - Sangeet Saha, Arnab Sarkar, Amlan Chakrabarti:
Spatio-Temporal Scheduling of Preemptive Real-Time Tasks on Partially Reconfigurable Systems. 71:1-71:26 - Jaume Abella, Maria Padilla, Joan del Castillo, Francisco J. Cazorla:
Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation. 72:1-72:29 - Zoran Salcic, HeeJong Park, Jürgen Teich, Avinash Malik, Muhammad Nadeem:
Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ. 73:1-73:25 - Lalatendu Behera, Purandar Bhaduri:
Time-Triggered Scheduling of Mixed-Criticality Systems. 74:1-74:25 - Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental Layer Assignment for Timing Optimization. 75:1-75:25
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