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2020 – today
- 2024
[j88]Bijay Raj Paudel
, Spyros Tragoudas:
Memristive Crossbar Array-Based Adversarial Defense Using Compression. IEEE Trans. Emerg. Top. Comput. 12(3): 864-877 (2024)- [c167]Danuka Malinda, Danushka Senarathna, Spyros Tragoudas:
Enhanced Distribution Matching for Multiclass Quantification. ICMLA 2024: 1238-1242 - 2023
- [c166]Vasileios Pentsos, Spyros Tragoudas:
A statistical approach to improve CNN classification accuracy. HPSR 2023: 1-5 - [c165]Danushka Senarathna, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit:
Detection and Quantization of Data Drift in Image Classification Neural Networks. HPSR 2023: 38-42 - [c164]Danushka Senarathna, Rezoan Ferdous, Spyros Tragoudas:
An Enhanced YOLO Failure Detection Method. ICMLA 2023: 958-965 - [c163]Bijay Raj Paudel, Spyros Tragoudas:
Adversarial Defense using Memristors and Input Preprocessing *. ISCAS 2023: 1-5 - [c162]Bijay Raj Paudel, Haibo Wang, Spyros Tragoudas, Omkar Rijal:
High Precision Winner-Take-All Circuit for Neural Networks. SOCC 2023: 1-6 - [c161]Danushka Senarathna, Spyros Tragoudas:
Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation. SOCC 2023: 1-6 - 2022
- [j87]Xiaoqian Chen, Lalit Gupta, Spyros Tragoudas:
Improving the Forecasting and Classification of Extreme Events in Imbalanced Time Series Through Block Resampling in the Joint Predictor-Forecast Space. IEEE Access 10: 121048-121079 (2022) - [j86]Krishna Prasad Gnawali, Spyros Tragoudas:
High-Speed Memristive Ternary Content Addressable Memory. IEEE Trans. Emerg. Top. Comput. 10(3): 1349-1360 (2022) - [c160]Bijay Raj Paudel, Spyros Tragoudas:
Compressed Learning in MCA Architectures to Tolerate Malicious Noise. IOLTS 2022: 1-8 - [c159]Bijay Raj Paudel, Vasileios Pentsos, Spyros Tragoudas:
On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks. ISQED 2022: 1-7 - [c158]Danushka Senarathna, Spyros Tragoudas:
Computation of Soft Error Rates Considering Test Pattern Sequences. ISQED 2022: 1-6 - [c157]Bijay Raj Paudel, Spyros Tragoudas:
The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays. ITC 2022: 519-523 - 2021
- [c156]Puneet Ramesh Savanur, Spyros Tragoudas:
A Fault Model to Detect Design Errors in Combinational Circuits. DFT 2021: 1-4 - [c155]Bijay Raj Paudel, Danushka Senarathna, Haibo Wang, Spyros Tragoudas, Yao Hu, Shengbing Jiang:
Predicting YOLO Misdetection by Learning Grid Cell Consensus. ICMLA 2021: 643-648 - [c154]Bijay Raj Paudel, Aashish Itani, Spyros Tragoudas:
Resiliency of SNN on Black-Box Adversarial Attacks. ICMLA 2021: 799-806 - [c153]Vasileios Pentsos, Bijay Raj Paudel, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit:
Improved CNN classification accuracy with the addition of shallow cascading CNNs. ICMLA 2021: 988-991 - 2020
- [j85]Adam Watkins, Spyros Tragoudas:
Radiation Hardened Latch Designs for Double and Triple Node Upsets. IEEE Trans. Emerg. Top. Comput. 8(3): 616-626 (2020) - [j84]Pavan Kumar Javvaji, Spyros Tragoudas:
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 163-173 (2020) - [c152]Basim Shanyour, Spyros Tragoudas:
Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors. IOLTS 2020: 1-3
2010 – 2019
- 2019
- [j83]Pavan Kumar Javvaji, Spyros Tragoudas:
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1196-1205 (2019) - [i1]Krishna Prasad Gnawali, Seyed Nima Mozaffari, Spyros Tragoudas:
Low Power Artificial Neural Network Architecture. CoRR abs/1904.02183 (2019) - 2018
- [j82]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 946-959 (2018) - [c151]Pavan Kumar Javvaji, Spyros Tragoudas:
A Method to Model Statistical Path Delays for Accurate Defect Coverage. DFT 2018: 1-6 - [c150]Puneet Ramesh Savanur, Spyros Tragoudas:
Threshold Voltage Extraction Using Static NBTI Aging. DFT 2018: 1-6 - [c149]Pavan Kumar Javvaji, Spyros Tragoudas, Ganesh Kondapuram:
Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection. ISCAS 2018: 1-5 - [c148]Pavan Kumar Javvaji, Basim Shanyour, Spyros Tragoudas:
Test set identification for improved delay defect coverage in the presence of statistical delays. ISQED 2018: 14-19 - [c147]Basim Shanyour, Spyros Tragoudas:
Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors. ITC 2018: 1-10 - [c146]Seyed Nima Mozaffari, Krishna Prasad Gnawali, Spyros Tragoudas:
An Aging Resilient Neural Network Architecture. NANOARCH 2018: 25-30 - 2017
- [j81]Stefan Leitner, Haibo Wang, Spyros Tragoudas:
Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges. J. Circuits Syst. Comput. 26(2): 1750035:1-1750035:21 (2017) - [j80]Ahish Mysore Somashekar, Spyros Tragoudas:
Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 325-335 (2017) - [j79]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
More Efficient Testing of Metal-Oxide Memristor-Based Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1018-1029 (2017) - [j78]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1063-1071 (2017) - [c145]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
A new method to identify threshold logic functions. DATE 2017: 934-937 - [c144]Ahish Mysore Somashekar, Spyros Tragoudas:
Efficient Critical Path Selection Under a Probabilistic Delay Model. ACM Great Lakes Symposium on VLSI 2017: 185-190 - [c143]Theodoros Toulas, Spyros Tragoudas:
Diagnosis with transition faults on embedded segments. IOLTS 2017: 25-27 - [c142]Pavan Kumar Javvaji, Spyros Tragoudas:
Efficient computation of the sensitization probability of a critical path considering process variations and path correlation. ISCAS 2017: 1-4 - [c141]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
Reducing power, area, and delay of threshold logic gates considering non-integer weights. ISCAS 2017: 1-4 - [c140]Adam Watkins, Spyros Tragoudas:
METS: A multiple event transient simulator. ISCAS 2017: 1-4 - [c139]Phaninder Alladi, Spyros Tragoudas:
Aging-aware critical paths for process related validation in the presence of NBTI. ISQED 2017: 445-448 - 2016
- [j77]Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for Delay Defects in Current Mode Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1903-1913 (2016) - [j76]Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi, Sreenivas Gangadhar:
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection. ACM Trans. Design Autom. Electr. Syst. 22(1): 17:1-17:21 (2016) - [c138]Adam Watkins, Spyros Tragoudas:
A Highly Robust Double Node Upset Tolerant latch. DFT 2016: 15-20 - [c137]Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis:
Identification of delay defects on embedded paths using one current sensor. DTIS 2016: 1-4 - [c136]Phaninder Alladi, Spyros Tragoudas:
Efficient selection of critical paths for delay defects in the presence of process variations. DTIS 2016: 1-6 - [c135]Adam Watkins, Spyros Tragoudas:
An Enhanced Analytical Electrical Masking Model for Multiple Event Transients. ACM Great Lakes Symposium on VLSI 2016: 369-372 - [c134]Stefan Leitner, Haibo Wang, Spyros Tragoudas:
Compressive image sensor technique with sparse measurement matrix. SoCC 2016: 223-228 - 2015
- [c133]Puneet Ramesh Savanur, Phaninder Alladi, Spyros Tragoudas:
A BIST approach for counterfeit circuit detection based on NBTI degradation. DFTS 2015: 123-126 - [c132]Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi:
Non-enumerative correlation-aware path selection. ICCD 2015: 629-634 - [c131]Joseph Lenox, Spyros Tragoudas:
Towards Trojan circuit detection with maximum state transition exploration. IOLTS 2015: 50-52 - [c130]Luke Pierce, Spyros Tragoudas:
Unreachable code identification for improved line coverage. ISQED 2015: 345-351 - [c129]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
Fast march tests for defects in resistive memory. NANOARCH 2015: 88-93 - 2014
- [j75]Luke Pierce, Spyros Tragoudas:
Nanopipelined threshold network synthesis. ACM J. Emerg. Technol. Comput. Syst. 10(2): 17:1-17:17 (2014) - [j74]Ashok Kumar Palaniswamy, Spyros Tragoudas:
Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms. ACM J. Emerg. Technol. Comput. Syst. 10(3): 21:1-21:32 (2014) - [j73]Pragyan (Sheela) Mohanty, Spyros Tragoudas:
Scalable Offline Searches in DNA Sequences. ACM J. Emerg. Technol. Comput. Syst. 11(2): 18:1-18:25 (2014) - [j72]Kedar Karmarkar, Spyros Tragoudas:
On-Chip Codeword Generation to Cope With Crosstalk. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 237-250 (2014) - [j71]Joseph Lenox, Spyros Tragoudas:
Adapting an Implicit Path Delay Grading Method for Parallel Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1965-1976 (2014) - [j70]Kedar Karmarkar, Spyros Tragoudas:
Error Correction Encoding for Tightly Coupled On-Chip Buses. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2571-2584 (2014) - [c128]Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas:
Diagnosis of segment delay defects with current sensing. DFT 2014: 122-127 - [c127]Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for transition faults of pipelined threshold logic circuits. DTIS 2014: 1-5 - [c126]Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, Spyros Tragoudas:
Adaptive compressive sensing for low power wireless sensors. ACM Great Lakes Symposium on VLSI 2014: 99-104 - [c125]Joseph Lenox, Spyros Tragoudas:
A novel parallel adaptation of an implicit path delay grading method. ACM Great Lakes Symposium on VLSI 2014: 217-222 - [c124]Phaninder Alladi, Spyros Tragoudas:
Aging-aware critical paths in deep submicron. IOLTS 2014: 184-185 - 2013
- [j69]Sreenivas Gangadhar, Spyros Tragoudas:
A Probabilistic Approach to Diagnose SETs in Sequential Circuits. J. Electron. Test. 29(3): 317-330 (2013) - [j68]Luke Pierce, Spyros Tragoudas:
Enhanced Secure Architecture for Joint Action Test Group Systems. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1342-1345 (2013) - [c123]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Low power and high speed current-mode memristor-based TLGs. DFTS 2013: 89-94 - [c122]Kedar Karmarkar, Spyros Tragoudas:
Error detection encoding for multi-threshold capture mechanism. IOLTS 2013: 92-97 - [c121]Ahish Mysore Somashekar, Spyros Tragoudas:
Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements. ISQED 2013: 481-486 - [c120]Dheepakkumaran Jayaraman, Spyros Tragoudas:
Performance validation through implicit removal of infeasible paths of the behavioral description. ISQED 2013: 552-557 - [c119]Dheepakkumaran Jayaraman, Spyros Tragoudas:
A method to determine the sensitization probability of a non-robustly testable path. ISQED 2013: 676-681 - 2012
- [j67]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. Ad Hoc Networks 10(3): 328-338 (2012) - [j66]Ashok Kumar Palaniswamy, Spyros Tragoudas:
An efficient heuristic to identify threshold logic functions. ACM J. Emerg. Technol. Comput. Syst. 8(3): 19:1-19:17 (2012) - [j65]Michael N. Skoufis, Spyros Tragoudas:
An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic. IEEE Trans. Computers 61(2): 187-198 (2012) - [c118]Sreenivas Gangadhar, Spyros Tragoudas:
Accurate calculation of SET propagation probability for hardening. DFT 2012: 104-108 - [c117]Adam Watkins, Spyros Tragoudas:
Transient pulse propagation using the Weibull distribution function. DFT 2012: 109-114 - [c116]Ashok Kumar Palaniswamy, Spyros Tragoudas:
A scalable threshold logic synthesis method using ZBDDs. ACM Great Lakes Symposium on VLSI 2012: 307-310 - [c115]Ahish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi:
Non-enumerative generation of statistical path delays for ATPG. ICCD 2012: 514-515 - [c114]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for an N-Input Current Mode Threshold Logic Gate. ISVLSI 2012: 344-349 - 2011
- [j64]Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Improved diagnosis using enhanced fault dominance. Integr. 44(3): 217-228 (2011) - [c113]Pragyan P. Mohanty, Spyros Tragoudas:
A Scalable Method for Identifying DNA Substrings Using Functions. BICoB 2011: 178-183 - [c112]Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis:
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. DFT 2011: 131-138 - [c111]Sreenivas Gangadhar, Spyros Tragoudas:
A Probabilistic Approach to Diagnose SETs. DFT 2011: 261-267 - [c110]Kedar Karmarkar, Spyros Tragoudas:
Error correction encoding for multi-threshold capture mechanism. IOLTS 2011: 157-162 - [c109]Luke Pierce, Spyros Tragoudas:
Multi-level secure JTAG architecture. IOLTS 2011: 208-209 - [c108]Dheepakkumaran Jayaraman, Spyros Tragoudas:
Occurrence probability analysis of a path at the architectural level. ISQED 2011: 464-468 - [c107]Sreenivas Gangadhar, Spyros Tragoudas:
An analytical method for estimating SET propagation. VTS 2011: 197-202 - 2010
- [j63]Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Scan Shift Power Reduction by Gating Internal Nodes. J. Low Power Electron. 6(2): 311-319 (2010) - [j62]Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis:
A Data Capturing Method for Buses on Chip. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1631-1641 (2010) - [j61]Rajsekhar Adapa, Spyros Tragoudas:
Techniques to Prioritize Paths for Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 658-661 (2010) - [j60]Edward Flanigan, Spyros Tragoudas:
Identification of Delay Measurable PDFs Using Linear Dependency Relationships. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1011-1015 (2010) - [c106]Kedar Karmarkar, Spyros Tragoudas:
Scalable codeword generation for coupled buses. DATE 2010: 729-734 - [c105]Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Gating internal nodes to reduce power during scan shift. ACM Great Lakes Symposium on VLSI 2010: 79-84 - [c104]Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas:
Scalable identification of threshold logic functions. ACM Great Lakes Symposium on VLSI 2010: 269-274 - [c103]Sreenivas Gangadhar, Spyros Tragoudas:
Probabilistic methods for the impact of an SET in combinational logic. IOLTS 2010: 41-46 - [c102]Michael N. Skoufis, Spyros Tragoudas:
On-line detection of random voltage perturbations in buses with multiple-threshold receivers. IOLTS 2010: 249-254 - [c101]Sreenivas Gangadhar, Spyros Tragoudas:
A novel probabilistic SET propagation method. ISQED 2010: 258-263
2000 – 2009
- 2009
- [c100]Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman:
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. VTS 2009: 140-145 - [e1]Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor:
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009. IEEE Computer Society 2009, ISBN 978-0-7695-3839-6 [contents] - 2008
- [j59]Kyriakos Christou, Maria K. Michael, Spyros Tragoudas:
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. J. Electron. Test. 24(1-3): 203-222 (2008) - [j58]Arkan Abdulrahman, Spyros Tragoudas:
Low-power multi-core ATPG to target concurrency. Integr. 41(4): 459-473 (2008) - [j57]Chunrong Song, Spyros Tragoudas:
Identification of Critical Executable Paths at the Architectural Level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2291-2302 (2008) - [c99]Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas:
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. DFT 2008: 176-183 - [c98]Rajsekhar Adapa, Spyros Tragoudas:
Prioritization of Paths for Diagnosis. DFT 2008: 474-481 - [c97]Sreenivas Gangadhar, Michael N. Skoufis, Spyros Tragoudas:
Propagation of Transients Along Sensitizable Paths. IOLTS 2008: 129-134 - [c96]Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas:
A Novel Test Generation Methodology for Adaptive Diagnosis. ISQED 2008: 242-245 - [c95]Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas:
A High-Performance Bus Architecture for Strongly Coupled Interconnects. ISQED 2008: 407-410 - [c94]Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas:
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. ISQED 2008: 633-636 - [c93]Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas:
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. ITC 2008: 1-10 - [c92]Manoj Kumar Goparaju, Spyros Tragoudas:
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. VTS 2008: 323-328 - [p2]Dimitri Kagaris, Spyros Tragoudas:
Graph Theory and Algorithms. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j56]Khadija Jirari Stewart, Spyros Tragoudas:
Managing the power resources of sensor networks with performance considerations. Comput. Commun. 30(5): 1122-1135 (2007) - [j55]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
High-Quality Transition Fault ATPG for Small Delay Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 983-989 (2007) - [j54]Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis:
Speedups in embedded systems with a high-performance coprocessor datapath. ACM Trans. Design Autom. Electr. Syst. 12(3): 35:1-35:22 (2007) - [c91]Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas:
Glitch Control with Dynamic Receiver Threshold Adjustment. ISQED 2007: 410-415 - [c90]Manoj Kumar Goparaju, Spyros Tragoudas:
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. ISQED 2007: 420-425 - [c89]Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov:
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. ISQED 2007: 717-722 - [c88]Edward Flanigan, Spyros Tragoudas:
Enhanced Identification of Strong Robustly Testable Paths. ISQED 2007: 729-736 - [c87]Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov:
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. VLSI Design 2007: 805-812 - [c86]Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Accelerating Diagnosis via Dominance Relations between Sets of Faults. VTS 2007: 219-224 - 2006
- [j53]Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose:
InTeRail: A Test Architecture for Core-Based SOCs. IEEE Trans. Computers 55(2): 137-149 (2006) - [j52]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A high-performance data path for synthesizing DSP kernels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1154-1162 (2006) - [j51]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2954-2964 (2006) - [j50]Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3026-3035 (2006) - [j49]Saravanan Padmanaban, Spyros Tragoudas:
Implicit grading of multiple path delay faults. ACM Trans. Design Autom. Electr. Syst. 11(2): 346-361 (2006) - [c85]Kyriakos Christou, Maria K. Michael, Spyros Tragoudas:
Implicit Critical PDF Test Generation with Maximal Test Efficiency. DFT 2006: 50-58 - [c84]Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas:
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. DFT 2006: 318-326 - [c83]Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. IOLTS 2006: 43-50 - [c82]Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Sub-faults identification for collapsing in diagnosis. ISCAS 2006 - [c81]Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas:
Minimizing FPGA Reconfiguration Data at Logic Level. ISQED 2006: 219-224 - [c80]Arkan Abdulrahman, Spyros Tragoudas:
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. ISQED 2006: 300-305 - [c79]Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Evaluation of Collapsing Methods for Fault Diagnosis. ISQED 2006: 439-444 - [c78]Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas:
An Improved Method for Identifying Linear Dependencies in Path Delay Faults. ISQED 2006: 457-462 - [c77]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Exact At-speed Delay Fault Grading in Sequential Circuits. ITC 2006: 1-10 - [c76]Khadija Jirari Stewart, Spyros Tragoudas:
Interconnect Testing for Networks on Chips. VTS 2006: 100-107 - 2005
- [j48]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. J. Circuits Syst. Comput. 14(4): 877-893 (2005) - [j47]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Low Power Test Generation for Path Delay Faults. J. Low Power Electron. 1(2): 194-205 (2005) - [j46]Saravanan Padmanaban, Spyros Tragoudas:
Efficient identification of (critical) testable path delay faults using decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 77-87 (2005) - [j45]Spyros Tragoudas, Vijay Nagarandal:
On-chip embedding mechanisms for large sets of vectors for delay test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 488-497 (2005) - [j44]M. Moiz Khan, Spyros Tragoudas:
Rewiring for watermarking digital circuit netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1132-1137 (2005) - [j43]Maria K. Michael, Spyros Tragoudas:
Function-based compact test pattern generation for path delay faults. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 996-1001 (2005) - [c75]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE 2005: 990-995 - [c74]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
A security protocol for sensor networks. GLOBECOM 2005: 5 - [c73]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Low power test generation for path delay faults using stability functions. ACM Great Lakes Symposium on VLSI 2005: 8-12 - [c72]Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Test set enhancement for quality transition faults using function-based methods. ACM Great Lakes Symposium on VLSI 2005: 182-187 - [c71]Maria K. Michael, Kyriakos Christou, Spyros Tragoudas:
Towards finding path delay fault tests with high test efficiency using ZBDDs. ICCD 2005: 464-467 - [c70]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Quality Transition Fault Tests Suitable for Small Delay Defects. ICCD 2005: 468-470 - [c69]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Design and Evaluation of a Security Scheme for Sensor Networks. ISQED 2005: 197-201 - [c68]M. Welling, Spyros Tragoudas, Haibo Wang:
A Minimum Cut Based Re-Synthesis Approach. ISQED 2005: 202-207 - [c67]Themistoklis Haniotakis, Spyros Tragoudas, G. Pani:
Reduced Test Application Time Based on Reachability Analysis. ISQED 2005: 232-237 - [c66]Maria K. Michael, Stelios Neophytou, Spyros Tragoudas:
Functions for Quality Transition Fault Tests. ISQED 2005: 327-332 - [c65]Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas:
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. VLSI Design 2005: 673-676 - 2004
- [j42]Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas:
A unified framework for generating all propagation functions for logic errors and events. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 980-986 (2004) - [j41]J. V. Deodhar, Spyros Tragoudas:
Implicit deductive fault simulation for complex delay fault models. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 636-641 (2004) - [c64]Saravanan Padmanaban, Spyros Tragoudas:
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. DATE 2004: 50-55 - [c63]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM 2004: 275-276 - [c62]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA 2004: 252 - [c61]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL 2004: 868-873 - [c60]Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas:
Low power ATPG for path delay faults. ACM Great Lakes Symposium on VLSI 2004: 389-392 - [c59]Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas:
Security enhancement through multiple path transmission in ad hoc networks. ICC 2004: 4187-4191 - [c58]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis:
A high performance data-path to accelerate DSP kernels. ICECS 2004: 495-498 - [c57]M. Moiz Khan, Spyros Tragoudas:
Rewiring for Watermarking Digital Circuits. ISQED 2004: 143-148 - [c56]Saravanan Padmanaban, Spyros Tragoudas:
An Adaptive Path Delay Fault Diagnosis Methodology. ISQED 2004: 491-496 - [c55]Saravanan Padmanaban, Spyros Tragoudas:
A Critical Path Selection Method for Delay Testing. ITC 2004: 232-241 - [c54]Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas:
On-line Testing Field Programmable Analog Array Circuits. ITC 2004: 1340-1348 - [c53]Arkan Abdulrahman, Spyros Tragoudas:
Compact ATPG for Concurrent SOC Testing. MTV 2004: 16-21 - [c52]M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu:
Identification of Gates for Covering all Critical Paths. MTV 2004: 92-96 - [c51]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS 2004: 652-661 - [c50]Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis:
A Novel Data-Path for Accelerating DSP Kernels. SAMOS 2004: 363-372 - 2003
- [j40]Dimitri Kagaris, Spyros Tragoudas:
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. J. Electron. Test. 19(3): 233-244 (2003) - [j39]Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas:
Exact path delay fault coverage with fundamental ZBDD operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 305-316 (2003) - [j38]Saravanan Padmanaban, Spyros Tragoudas:
An implicit path-delay fault diagnosis methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1399-1408 (2003) - [j37]Spyros Tragoudas, N. Denny:
Path delay fault testing using test points. ACM Trans. Design Autom. Electr. Syst. 8(1): 1-10 (2003) - [c49]Saravanan Padmanaban, Spyros Tragoudas:
Non-Enumerative Path Delay Fault Diagnosis . DATE 2003: 10322-10327 - [c48]Dimitri Kagaris, Spyros Tragoudas:
InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. IOLTS 2003: 219-224 - [c47]Maria K. Michael, Spyros Tragoudas:
Generation of Hazard Identification Functions. ISQED 2003: 419-424 - 2002
- [j36]Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas:
An efficient algorithm for finding a path subject to two additive constraints. Comput. Commun. 25(3): 225-238 (2002) - [j35]Dimitrios Kagaris, Spyros Tragoudas:
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. J. Electron. Test. 18(3): 305-313 (2002) - [j34]Spyros Tragoudas, Yaakov L. Varol:
Disjoint Paths with Length Constraints. Int. J. Comput. Their Appl. 9(3): 158-166 (2002) - [j33]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 859-866 (2002) - [j32]Dimitrios Kagaris, Spyros Tragoudas:
On the nonenumerative path delay fault simulation problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1095-1101 (2002) - [j31]Maria K. Michael, Spyros Tragoudas:
ATPG tools for delay faults at the functional level. ACM Trans. Design Autom. Electr. Syst. 7(1): 33-57 (2002) - [c46]Saravanan Padmanaban, Spyros Tragoudas:
Exact Grading of Multiple Path Delay Faults. DATE 2002: 84-88 - 2001
- [j30]Dimitrios Kagaris, Spyros Tragoudas:
Computational analysis of counter-based schemes for VLSI test pattern generation. Discret. Appl. Math. 110(2-3): 227-250 (2001) - [j29]Dimitrios Kagaris, Spyros Tragoudas:
Von Neumann hybrid cellular automata for generating deterministic test sequences. ACM Trans. Design Autom. Electr. Syst. 6(3): 308-321 (2001) - [j28]Spyros Tragoudas:
The most reliable data-path transmission. IEEE Trans. Reliab. 50(3): 281-285 (2001) - [c45]Dimitri Kagaris, Spyros Tragoudas:
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. IOLTW 2001: 75-79 - [c44]Jayant Deodhar, Spyros Tragoudas:
Color Counting and its Application to Path Delay Fault Coverage. ISQED 2001: 378-383 - [c43]Maria K. Michael, Spyros Tragoudas:
ATPG for Path Delay Faults without Path Enumeration. ISQED 2001: 384-389 - [c42]Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas:
Exact path delay grading with fundamental BDD operations. ITC 2001: 642-651 - 2000
- [j27]Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar:
Test-set partitioning for multi-weighted random LFSRs. Integr. 30(1): 65-75 (2000) - [c41]Dimitrios Kagaris, Spyros Tragoudas:
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. ICCD 2000: 42-47 - [c40]Dimitri Kagaris, Spyros Tragoudas:
Methods for on-chip embedding of path delay test vectors. ISCAS 2000: 84-87 - [c39]Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas:
An efficient algorithm for finding a path subject to two additive constraints. SIGMETRICS 2000: 318-327 - [c38]Spyros Tragoudas:
Power dissipation component of a management protocol for ad-hoc networks. WCNC 2000: 555-559 - [c37]Spyros Tragoudas, S. Dimitrova:
Routing with energy considerations in mobile ad-hoc networks. WCNC 2000: 1258-1261
1990 – 1999
- 1999
- [j26]Dimitri Kagaris, Spyros Tragoudas:
Maximum weighted independent sets on transitive graphs and applications1. Integr. 27(1): 77-86 (1999) - [j25]Dimitrios Kagaris, Grammati E. Pantziou, Spyros Tragoudas, Christos D. Zaroliagis:
Transmissions in a network with capacities and delays. Networks 33(3): 167-174 (1999) - [j24]Dimitrios Kagaris, Spyros Tragoudas:
On the design of optimal counter-based schemes for test set embedding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 219-230 (1999) - [j23]Spyros Tragoudas, Dimitrios Karayiannis:
A fast nonenumerative automatic test pattern generator for pathdelay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1050-1057 (1999) - [j22]Spyros Tragoudas, Ralf Münzenberger, Kenneth J. Danhof:
Board-level partitioning for partial scan using fuzzy logic. IEEE Trans. Fuzzy Syst. 7(2): 241-249 (1999) - [c36]Spyros Tragoudas, Yaakov L. Varol:
Disjoint paths with length constraints. CATA 1999: 277-280 - [c35]Spyros Tragoudas, Maria K. Michael:
ATPG Tools for Delay Faults at the Functional Level. DATE 1999: 631- - [c34]Spyros Tragoudas, N. Denny:
Testing for Path Delay Faults Using Test Points. DFT 1999: 86-94 - [c33]Dimitrios Kagaris, Spyros Tragoudas:
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. DFT 1999: 130-138 - [c32]Spyros Tragoudas, Maria K. Michael:
Functional ATPG for Delay Faults. Great Lakes Symposium on VLSI 1999: 16-19 - [c31]Spyros Tragoudas:
The most reliable data path transmission. IPCCC 1999: 15-19 - [c30]Dimitrios Kagaris, Spyros Tragoudas:
Embedded cores using built-in mechanisms. ISCAS (1) 1999: 23-26 - [c29]Spyros Tragoudas:
Accurate path delay fault coverage is feasible. ITC 1999: 201-210 - [r1]Spyros Tragoudas:
CAD Tools for BIST/DFT and Delay Faults. The VLSI Handbook 1999 - 1998
- [j21]Dimitrios Karayiannis, Spyros Tragoudas:
Clustering Network Modules with Different Implementations for Delay Minimization. VLSI Design 7(1): 1-13 (1998) - [j20]Dimitrios Karayiannis, Spyros Tragoudas:
Timing-Driven Circuit Implementation. VLSI Design 7(2): 211-224 (1998) - [c28]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
On-Chip Test Embedding for Multi-Weighted Random LFSRs. DFT 1998: 135- - [c27]Dimitrios Karayiannis, Spyros Tragoudas:
A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. VTS 1998: 440-445 - 1997
- [j19]Spyros Tragoudas, Dimitrios Karayiannis:
Implementing and clustering modules with complex delays. Integr. 22(1-2): 39-57 (1997) - [j18]Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis:
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 309-315 (1997) - [c26]Dimitrios Kagaris, Spyros Tragoudas:
Cellular automata for generating deterministic test sequences. ED&TC 1997: 77-81 - [c25]Dimitrios Kagaris, Spyros Tragoudas:
Maximum independent sets on transitive graphs and their applications in testing and CAD. ICCAD 1997: 736-740 - [c24]Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis:
Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. ICCD 1997: 366-371 - 1996
- [j17]Spyros Tragoudas:
Improved Approximations for the Minimum-Cut Ratio and the Flux. Math. Syst. Theory 29(2): 157-167 (1996) - [j16]Dimitrios Kagaris, Spyros Tragoudas:
Retiming-Based Partial Scan. IEEE Trans. Computers 45(1): 75-87 (1996) - [j15]Spyros Tragoudas:
Min-Cut Partitioning on Underlying Tree and Graph Structures. IEEE Trans. Computers 45(4): 470-474 (1996) - [j14]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
On the Use of Counters for Reproducing Deterministic Test Sets. IEEE Trans. Computers 45(12): 1405-1419 (1996) - [j13]Dimitrios Kagaris, Spyros Tragoudas:
A fast algorithm for minimizing FPGA combinational and sequential modules. ACM Trans. Design Autom. Electr. Syst. 1(3): 341-351 (1996) - [c23]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
Deterministic Test Pattern Reproduction by a Counter. ED&TC 1996: 37-41 - [c22]Dimitrios Kagaris, Spyros Tragoudas:
A multiseed counter TPG with performance guarantee. ICCD 1996: 34-39 - [c21]D. Kuguris, Spyros Tragoudas:
FPGA Module Minimization. ICCD 1996: 566-571 - [c20]Dimitrios Karayiannis, Spyros Tragoudas:
ATPD: An Automatic Test Pattern Generator for Path Delay Faults. ITC 1996: 443-452 - [c19]Dimitrios Kagaris, Spyros Tragoudas:
Generating deterministic unordered test patterns with counters. VTS 1996: 374-379 - [c18]Spyros Tragoudas, Yaakov L. Varol:
Computing Disjoint Path with Lenght Constraints. WG 1996: 375-389 - 1995
- [j12]Dimitrios Kagaris, Spyros Tragoudas:
Avoiding linear dependencies in LFSR test pattern generators. J. Electron. Test. 6(2): 229-241 (1995) - [j11]James Haralambides, Spyros Tragoudas:
Bipartitioning into Overlapping Sets. Int. J. Found. Comput. Sci. 6(1): 67-88 (1995) - [j10]Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Tardos, Spyros Tragoudas:
Fast Approximation Algorithms for Multicommodity Flow Problems. J. Comput. Syst. Sci. 50(2): 228-243 (1995) - [j9]Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia:
Pseudo-exhaustive built-in TPG for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1160-1171 (1995) - [c17]Dimitrios Karayiannis, Spyros Tragoudas:
Uniform area timing-driven circuit implementation. Great Lakes Symposium on VLSI 1995: 2-7 - [c16]Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis:
Quickest paths: parallelization and dynamization . HICSS (2) 1995: 39-40 - [c15]Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis:
On the Computation of Fast Data Transmissions in Networks with Capacities and Delays. WADS 1995: 291-302 - 1994
- [j8]James Haralambides, Spyros Tragoudas:
The Problem of Partitioning with Duplications and its Applications. Int. J. Artif. Intell. Tools 3(3): 395-406 (1994) - [j7]Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas:
A method for pseudo-exhaustive test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1170-1178 (1994) - [j6]Spyros Tragoudas:
On Channel Routing Problems With Interchangeable Terminals. VLSI Design 2(1): 51-68 (1994) - [c14]Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas:
Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI 1994: 76-79 - [c13]Dimitrios Kagaris, Spyros Tragoudas:
Retiming algorithms with application to VLSI testability. Great Lakes Symposium on VLSI 1994: 216-221 - [c12]Spyros Tragoudas:
An improved algorithm for the generalized min-cut partitioning problem. Great Lakes Symposium on VLSI 1994: 242-247 - [c11]Dimitrios Kagaris, Spyros Tragoudas:
A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. ICCD 1994: 292-295 - [c10]Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani:
High Performance Over-the-Cell Routing. VLSI Design 1994: 137-142 - [c9]Dimitrios Kagaris, Spyros Tragoudas:
A design for testability technique for test pattern generation with LFSRs. VTS 1994: 68-73 - 1993
- [j5]Antonios Symvonis, Spyros Tragoudas:
Searching a Pseudo 3-Sided Solid Orthoconvex Grid. Int. J. Found. Comput. Sci. 4(4): 325-353 (1993) - [j4]Spyros Tragoudas, Ioannis G. Tollis:
River routing and density minimization for channels with interchangeable terminals. Integr. 15(2): 151-178 (1993) - [j3]Dimitrios Kagaris, Spyros Tragoudas:
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 526-536 (1993) - [c8]Dimitrios Kagaris, Spyros Tragoudas:
Partial Scan with Retiming. DAC 1993: 249-254 - [c7]Spyros Tragoudas:
Minmax-cut graph partitioning problems. Great Lakes Symposium on VLSI 1993: 100-104 - [c6]Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia:
Pseudoexhaustive BIST for Sequential Circuits. ICCD 1993: 523-527 - [p1]Fillia Makedon, Spyros Tragoudas:
Approximate solutions for Graph and Hypergraph Partitioning. Algorithmic Aspects of VLSI Layout 1993: 133-166 - 1992
- [j2]Spyros Tragoudas, Fillia Makedon, Robert Farell:
Circuit partitioning into small sets. Microprocess. Microsystems 16(9): 481-491 (1992) - [c5]Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas:
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. ICCD 1992: 358-364 - [c4]Antonios Symvonis, Spyros Tragoudas:
Searching a Solid Pseudo 3-Sided Orthoconvex Grid. ISAAC 1992: 188-197 - 1991
- [j1]Panayiotis E. Pintelas, Spyros Tragoudas:
A comparative study of five language independent programming environments. J. Syst. Softw. 14(1): 3-15 (1991) - [c3]Spyros Tragoudas, R. Farrell, Fillia Makedon:
Circuit partitioning into small sets: a tool to support testing with further applications. EURO-DAC 1991: 518-522 - [c2]Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Tardos, Spyros Tragoudas:
Fast Approximation Algorithms for Multicommodity Flow Problems. STOC 1991: 101-111 - 1990
- [c1]Fillia Makedon, Spyros Tragoudas:
Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems. WG 1990: 140-153
Coauthor Index
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