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2020 – today
- 2021
[j11]Chun-Cheng Liu, Tao-Chuan Shih, Tun-Wen Pai, Chin-Hwa Hu
, Wen-Shyong Tzou:
Enhanced Over-Representation Analysis for the Differential Regulation of Birc5a and HIF2α-Knockdown Approaches. J. Comput. Biol. 28(7): 674-686 (2021)- 2020
- [c13]Chun-Cheng Liu, Tao-Chuan Shih, Tun-Wen Pai, Chin-Hwa Hu, Lee-Jyi Wang:
Enhanced Functional Pathway Annotations for Differentially Expressed Gene Clusters. ISBRA 2020: 352-363 - [c12]Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung:
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. ISSCC 2020: 118-120
2010 – 2019
- 2019
- [c11]Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman:
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. ISSCC 2019: 118-120 - 2017
- [c10]Chun-Cheng Liu, Mu-Chen Huang:
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter. ISSCC 2017: 466-467 - 2016
- [j10]Chun-Cheng Liu, Mu-Chen Huang, Yu-Hsuan Tu:
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC. IEEE J. Solid State Circuits 51(12): 2941-2950 (2016) - [c9]Chun-Cheng Liu, Chien-Ming Chen, Cin-Han Yang, Tun-Wen Pai, Phaik-Eem Lim, Siew-Moi Phang, Sze-Wan Poong, Kok-Keong Lee:
Biological Pathway Analysis for De Novo Transcriptomes through Multiple Reference Species Selections. CISIS 2016: 210-214 - [c8]Chun-Cheng Liu:
27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS. ISSCC 2016: 462-463 - 2015
- [j9]Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin:
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. IEEE J. Solid State Circuits 50(11): 2645-2654 (2015) - [j8]Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu:
A 0.022 mm2 98.5 dB SNDR Hybrid Audio ΔΣ Modulator With Digital ELD Compensation in 28 nm CMOS. IEEE J. Solid State Circuits 50(11): 2655-2664 (2015) - [c7]Chun-Cheng Liu, Chien-Ming Chen, Tun-Wen Pai, Hsin-Yiu Chou, Hui-Huang Hsu:
Exclusive Genomic Pathway Analysis for Groupers Infected by Different Iridovirus. CISIS 2015: 508-512 - 2014
- [c6]Chun-Cheng Liu:
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS. A-SSCC 2014: 77-80 - [c5]Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu:
A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS. A-SSCC 2014: 317-320 - 2013
- [j7]Li-Qun Hou, Xue-Feng Zhao, Rui-Cong Han, Chun-Cheng Liu:
Optimal Sensor Placement for Stay Cable Damage Identification of Cable-Stayed Bridge under Uncertainty. Int. J. Distributed Sens. Networks 9 (2013) - [j6]Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang:
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 570-581 (2013) - [j5]Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 584-588 (2013) - 2012
- [j4]Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. IEEE J. Solid State Circuits 47(11): 2783-2795 (2012) - 2011
- [c4]Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang:
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. ASP-DAC 2011: 231-236 - [c3]Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu:
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. A-SSCC 2011: 69-72 - 2010
- [j3]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE J. Solid State Circuits 45(4): 731-740 (2010) - [j2]Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang:
A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 163-167 (2010) - [j1]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1829-1837 (2010) - [c2]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai:
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC 2010: 386-387
2000 – 2009
- 2009
- [c1]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC 2009: 80-81
Coauthor Index
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