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ORCIDISSCC 2016: San Francisco, CA, USA
- 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. IEEE 2016, ISBN 978-1-4673-9466-6
- Laura Chizuko Fujino:
Reflections. 4 - Kevin Zhang:
Foreword: Silicon systems for the Internet of Everything. 5 - Anantha P. Chandrakasan, Kevin Zhang:
Session 1 overview: Plenary session. 6-7 - William M. Holt:
1.1 Moore's law: A path going forward. 8-13 - Sophie V. Vandebroek:
1.2 Three pillars enabling the Internet of Everything: Smart everyday objects, information-centric networks, and automated real-time insights. 14-20 - Seizo Onoe:
1.3 Evolution of 5G mobile technology toward 1 2020 and beyond. 23-28 - Lars Reger:
1.4 The road ahead for securely-connected cars. 29-33 - Ahmad Mirzaei, Hyunchol Shin:
Session 2 overview: RF frequency synthesis techniques. 34-35 - Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
:
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. 36-37 - Abhishek Agrawal, Arun Natarajan:
2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays. 38-39 - Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong:
2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL. 40-41 - Tino Copani, Claudio Asero, Matteo Colombo, Paolo Aliberti, Giuseppe Martino, Francesco Clerici:
2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applications. 42-43 - David Murphy, Hooman Darabi:
2.5 A complementary VCO for IoE that achieves a 195dBc/Hz FOM and flicker noise corner of 200kHz. 44-45 - Rouzbeh Kananizadeh, Omeed Momeni:
2.6 A 190.5GHz mode-switching VCO with 20.7% continuous tuning range and maximum power of -2.1dBm in 0.13µm BiCMOS. 46-47 - Jun Yin, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. 48-49 - Dongseok Shin, Sanjay Raman, Kwang-Jin Koh:
2.8 A mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13µm CMOS. 50-51 - Sebastian Sievert, Ofir B. Degani, Assaf Ben Bassat, Rotem Banin, Ashoke Ravi, Bernd-Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel:
2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS. 52-54 - Hyeon-Min Bae, Ajith Amerasekera:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links. 54-55 - Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli:
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. 56-57 - Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo-Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao:
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS. 58-59 - Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. 60-61 - Karthik Gopalakrishnan, Alan Ren, Amber Tan, Arash Farhood, Arun Tiruvur, Belal Helal, Chang-Feng Loi, Chris Jiang, Halil Cirit, Irene Quek, Jamal Riani, James Gorecki, Jennifer Wu, Jorge Pernillo, Lawrence Tse, Michael Q. Le, Mohammad Ranjbar, Pui-Shan Wong, Pulkit Khandelwal, Rajesh Narayanan, Ravindran Mohanavelu, Sameer Herlekar, Sudeep Bhoja, Vlad Shvydun:
3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS. 62-63 - Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. 64-65 - Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, Andrea Mazzanti:
3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI. 66-67 - Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang:
3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. 68-70 - Mahesh Mehendale, Luke Shin:
Session 4 overview: Digital processors. 70-71 - Eyal Fayneh, Marcelo Yuffe, Ernest Knoll, Michael Zelikson, Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme:
4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance. 72-73 - Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger:
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. 74-75 - Hugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko:
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. 76-77 - Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. 78-79 - Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita:
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. 80-81 - Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. 82-83 - Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong Jung Lin, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang:
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. 84-86 - Marco Berkhout, Tim Piessens:
Session 5 overview: Analog techniques. 86-87 - Vadim Ivanov, Munaf Shaik:
5.1 A 10MHz-bandwidth 4µs-large-signal-settling 6.5nV/√Hz-noise 2µV-offset chopper operational amplifier. 88-89 - Wen-Chieh Wang, Yu-Hsin Lin:
5.2 A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W fully differential class-D audio amplifier with PWM common-mode control. 90-91 - Mikkel Hoyerby, Jorgen Kragh Jakobsen, Jesper Midtgaard, Thomas Holm Hansen, Allan Nogueras Nielsen, Hans Hasselby-Andersen:
5.3 A 2×70W monolithic five-level Class-D audio power amplifier. 92-93 - Frank M. Yaul, Anantha P. Chandrakasan:
5.4 A sub-µW 36nV/√Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2V-supply input stage. 94-95 - Hariprasad Chandrakumar, Dejan Markovic:
5.5 A 2µW 40mVpp linear-input-range chopper- stabilized bio-signal amplifier with boosted input impedance of 300MΩ and electrode-offset filtering. 96-97 - Marco Sautto, Fabio Quaglia, Giulio Ricotti, Andrea Mazzanti:
5.6 A 420µW 100GHz-GBW CMOS Programmable-Gain Amplifier leveraging the cross-coupled pair regeneration. 98-99 - Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya:
5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage. 100-101 - Tae-Kwang Jang, Myungjoon Choi, Seokhyeon Jeong, Suyoung Bang, Dennis Sylvester, David T. Blaauw:
5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme. 102-103 - Danielle Griffith, James Murdock, Per Torstein Røine:
5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injection. 104-105 - Junghyup Lee, Arup K. George, Minkyu Je:
5.10 A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOS. 106-108 - Jun Deguchi, David Stoppa:
Session 6 overview: Image sensors. 108-109 - Kazuko Nishimura, Yoshihiro Sato, Junji Hirase, Ryota Sakaida, Masaaki Yanagida, Tokuhiko Tamaki, Masayuki Takase, Hidenari Kanehara, Masashi Murakami, Yasunori Inoue:
6.1 An over 120dB simultaneous-capture wide-dynamic-range 1.6e- ultra-low-reset-noise organic-photoconductive-film CMOS image sensor. 110-111 - Sanshiro Shishido, Yasuo Miyake, Yoshiaki Sato, Tokuhiko Tamaki, Naoki Shimasaki, Yoshihiro Sato, Masashi Murakami, Yasunori Inoue:
6.2 210ke- Saturation signal 3µm-pixel variable-sensitivity global-shutter organic photoconductive image sensor for motion capture. 112-113 - Jan Bogaerts, Raf Lafaille, Marc Borremans, Jia Guo, Bart Ceulemans, Guy Meynants, Navid Sarhangnejad, Gavril Arsinte, Victor Statescu, Sonja van der Groen:
6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications. 114-115 - Hirofumi Totsuka, Toshiki Tsuboi, Takashi Muto, Daisuke Yoshida, Yasushi Matsuno, Masanobu Ohmura, Hidekazu Takahashi, Katsuhito Sakurai, Takeshi Ichikawa, Hiroshi Yuzurihara, Shunsuke Inoue:
6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers. 116-117 - Matteo Perenzoni, Daniele Perenzoni, David Stoppa:
6.5 A 64×64-pixel digital silicon photomultiplier direct ToF sensor with 100Mphotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6km for spacecraft navigation and landing. 118-119 - Mitsuyoshi Mori, Yusuke Sakata, Manabu Usuda, Sejii Yamahira, Shigetaka Kasuga, Yutaka Hirose, Yoshihisa Kato, Tsuyoshi Tanaka:
6.6 A 1280×720 single-photon-detecting image sensor with 100dB dynamic range using a sensitivity-boosting technique. 120-121 - Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura:
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. 122-123 - Charles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang, Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh:
6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias. 124-125 - Toshiki Arai, Toshio Yasue, Kazuya Kitamura, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Satoshi Aoyama, Ming-Chieh Hsu, Yuichiro Yamashita, Hirofumi Sumi, Shoji Kawahito:
6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters. 126-128 - Sungdae Choi, Jin-Man Han:
Session 7 overview: Nonvolatile memory solutions. 128-129 - Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong-Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doo-Gon Kim, Young-Sun Min, Moosung Kim, Ansoo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doosub Lee, Hyunggon Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. 130-131 - Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. 132-133 - Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. 134-135 - Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang:
7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. 136-137 - Seungjae Lee, Jin-Yub Lee, Il-Han Park, Jong-Yeol Park, Sung-Won Yun, Minsu Kim, Jong-Hoon Lee, Min-Seok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-No Im, Hyejin Yim, Kyung-Hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-Lo Ahn, Sung-Min Joe, Suyong Kim, Deok-kyun Woo, Jiyoon Park, Hyun Wook Park, Youngmin Kim, Jonghoon Park, Yongsu Choi, Makoto Hirano, Jeong-Don Ihm, Byunghoon Jeong, Seon-Kyoo Lee, Moosung Kim, Hokil Lee, Sungwhan Seo, Hongsoo Jeon, Chan-ho Kim, Hyunggon Kim, Jintae Kim, Yongsik Yim, Hoosung Kim, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. 138-139 - Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. 140-141 - Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo:
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. 142-144 - Eric Fluhr, Bing Sheu:
Session 8 overview: Low-power digital circuits. 144-145 - Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos:
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. 146-147 - Doyun Kim, Mingoo Seok:
8.2 Fully integrated low-drop-out regulator based on event-driven PI control. 148-149 - Yong-Jin Lee, Min-Yong Jung, Shashank Singh, Tae-Hwang Kong, Dae-Yong Kim, Kwang-Ho Kim, Sang-Ho Kim, Jae-Jin Park, Ho-Jin Park, Gyu-Hyeong Cho:
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors. 150-151 - Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. 152-153 - Wanyeong Jung, Junhua Gu, Paul D. Myers, Minseob Shim, Seokhyeon Jeong, Kaiyuan Yang, Myungjoon Choi, Zhiyoong Foo, Suyoung Bang, Sechang Oh, Dennis Sylvester, David T. Blaauw:
8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems. 154-155 - John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. 156-157 - Bohdan Karpinskyy, Yongki Lee, Yunhyeok Choi, Yongsoo Kim, Mijung Noh, Sanghyun Lee:
8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips. 158-160 - Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor. 160-162 - Ali Afsahi, Guang-Kaai Dehng:
Session 9 overview: High-performance wireless. 162-163 - Nikolaus Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, Himanshu Arora, Satish Uppathil, Scott Kaylor, A. Akour, V. Wang, M. Fares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, Charles K. Sestok, C. Fernando, Rajagopal K. A., S. Ramakrishnan, V. Sinari, V. Baireddy:
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth. 164-165 - Linxiao Zhang, Arun Natarajan, Harish Krishnaswamy:
9.2 A scalable 0.1-to-1.7GHz spatio-spectral-filtering 4-element MIMO receiver array with spatial notch suppression enabling digital beamforming. 166-167 - Jianxun Zhu, Peter R. Kinget:
9.3 A very-low-noise frequency-translational quadrature-hybrid receiver for carrier aggregation. 168-169 - Renaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin:
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. 170-171 - Zhiming Deng, Eric Lu, Edris Rostami, Dai Sieh, Dimitris Papadopoulos, Bryan Huang, Ray Chen, Hua Wang, W. H. Hsu, C. H. Wu, Osama Shana'a:
9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS. 172-173 - Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin:
9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. 174-175 - Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. 176-177 - Jin Zhou, Negar Reiskarimian, Harish Krishnaswamy:
9.8 Receiver with integrated magnetic-free N-path-filter-based non-reciprocal circulator and baseband self-interference cancellation for full-duplex wireless. 178-180 - Jaeha Kim, Roberto Nonis:
Session 10 overview: Advanced wireline transceivers and PLLs. 180-181 - Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh:
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. 182-183 - Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. 184-185 - Hui Pan, Junhua Tan, Evelyn Wenting Wang, Jingguang Wang, Karthik Swaminathan, Ramalingam Pandarinathan, Ramesh Pasagadugula, VamshiKrishna Yakkala, Mostafa Hammad, Karim Abdelhalim, Kaijun Li, Su Cui, Jing Wang, Ahmad Chini, Mehmet Tazebay, Suresh Venkatesan, Derek Tam, Ichiro Fujimori, Kambiz Vakilian:
10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS. 186-187 - Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Matsumoto, Hideyuki Suzuki, Norio Shoji:
10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture. 188-189 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. 190-191 - Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu:
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. 192-193 - Seojin Choi, Seyeon Yoo, Jaehyouk Choi:
10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. 194-195 - Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. 196-198 - Yong Ping Xu, Joseph Shor:
Session 11 overview: Sensors and displays. 198-199 - Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon:
11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. 200-201 - Hao-Yen Tang, Yipeng Lu, Fari Assaderagh, Mike Daneman, Xiaoyue Jiang, Martin Lim, Xi Li, Eldwin Jiaqiang Ng, Utkarsh Singhal, Julius M. Tsai, David A. Horsley, Bernhard E. Boser:
11.2 3D ultrasonic fingerprint sensor-on-a-chip. 202-203 - Junfeng Jiang, Kofi A. A. Makinwa:
11.3 A hybrid multipath CMOS magnetic sensor with 210µTrms resolution and 3MHz bandwidth for contactless current sensing. 204-205 - Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa:
11.4 1650µm2 thermal-diffusivity sensors with inaccuracies down to ±0.75°C in 40nm CMOS. 206-207 - David Ruffieux, Franz-Xaver Pengg, Nicola Scolari, Frédéric Giroud, Daniel Séverac, Thanh Le, Silvio Dalla Piazza, Olivier Aubry:
11.5 A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHz-DTCXO RTC module with an overall accuracy of µ1ppm and an all-digital 0.1ppm compensation-resolution scheme at 1Hz. 208-209 - Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong:
11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp. 210-211 - Jun-Suk Bang, Hyunsik Kim, Kye-Seok Yoon, Sang-Han Lee, Se-Hong Park, Ohjo Kwon, Choongsun Shin, Seonki Kim, Gyu-Hyeong Cho:
11.7 A load-aware pre-emphasis column driver with 27% settling-time reduction in ±18% panel-load RC delay variation for 240Hz UHD flat-panel displays. 212-213 - Behnam Behroozpour, Phillip A. M. Sandborn, Niels Quack, Tae Joon Seok, Yasuhiro Matsui, Ming C. Wu, Bernhard E. Boser:
11.8 Chip-scale electro-optical 3D FMCW lidar with 8µm ranging precision. 214-216 - Vadim Ivanov, Jaejin Park:
Session 12 overview: Efficient Power Conversion. 216-217 - Wanyeong Jung, Dennis Sylvester, David T. Blaauw:
12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback. 218-219 - Nicolas Butzen, Michiel Steyaert:
12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution. 220-221 - Chen Kong Teh, Atsushi Suzuki:
12.3 A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage range. 222-223 - Daniel Lutz, Peter Renz, Bernhard Wicht:
12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency. 224-225 - Jing Xue, Hoi Lee:
12.5 A 2MHz 12-to-100V 90%-efficiency self-balancing ZVS three-level DC-DC regulator with constant-frequency AOT V2 control and 5ns ZVS turn-on delay. 226-227 - Szu-Yu Huang, Kuan-Yu Fang, Yi-Wei Huang, Shih-Hsiung Chien, Tai-Haur Kuo:
12.6 Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimization. 228-229