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2020 – today
- 2021
[c19]Ying-Yao Huang, Chang-Tzu Lin, Wei-Lun Liang, Hung-Ming Chen:
Learning Based Placement Refinement to Reduce DRC Short Violations. VLSI-DAT 2021: 1-4
2010 – 2019
- 2019
- [c18]Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen:
More Effective Power Network Prototyping by Analytical and Centroid Learning. ISCAS 2019: 1-5 - 2017
- [c17]Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou:
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. ASP-DAC 2017: 549-553 - [c16]Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou:
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. ISVLSI 2017: 459-464 - 2016
- [c15]Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee:
A New Methodology for Noise Sensor Placement Based on Association Rule Mining. ACM Great Lakes Symposium on VLSI 2016: 81-86 - 2014
- [c14]Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai:
Improving power delivery network design by practical methodologies. ICCD 2014: 237-242 - [c13]Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. VLSI-DAT 2014: 1-4 - 2013
- [c12]Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. ASP-DAC 2013: 151-156 - [c11]Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Effective power network prototyping via statistical-based clustering and sequential linear programming. DATE 2013: 1701-1706 - [c10]Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai:
Enabling inter-die co-optimization in 3-D IC with TSVs. VLSI-DAT 2013: 1-4 - 2012
- [c9]Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Hierarchical power network synthesis for multiple power domain designs. ISQED 2012: 477-482 - [c8]Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou:
3-D centric technology and realization with TSV. VLSI-DAT 2012: 1-4 - 2011
- [c7]Ding-Ming Kwai, Chang-Tzu Lin:
3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. ISQED 2011: 129-134 - 2010
- [c6]Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192
2000 – 2009
- 2007
- [j2]De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng:
Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. Artif. Intell. 20(6): 821-830 (2007) - [c5]Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng:
Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS 2007: 2028-2031 - 2006
- [j1]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. J. Circuits Syst. Comput. 15(1): 107-128 (2006) - 2005
- [c4]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho:
Modem floorplanning with abutment and fixed-outline constraints. ISCAS (6) 2005: 6214-6217 - 2004
- [c3]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
Robust fixed-outline floorplanning through evolutionary search. ASP-DAC 2004: 42-44 - 2003
- [c2]De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang:
Non-slicing floorplans with boundary constraints using generalized polish expression. ASP-DAC 2003: 342-345 - 2002
- [c1]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
GPE: A New Representation for VLSI Floorplan Problem. ICCD 2002: 42-44
Coauthor Index
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