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ORCIDYoung-Su Kwon
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2020 – today
- 2023
[c38]Youngsu Kwon, Jinho Han, Yong Cheol Peter Cho, Juyeob Kim, Jaehoon Chung, Jaewoong Choi, Sujin Park, Igyeong Kim, Hyunjeong Kwon, Jinkyu Kim, Hyunmi Kim, Won Jeon, Young-Deuk Jeon, Min-Hyung Cho, Minseok Choi:
Chiplet Heterogeneous-Integration AI Processor. ICEIC 2023: 1-2- [c37]Sujin Park, Yi-Gyeong Kim, Young-Deuk Jeon, Min-Hyung Cho, Jinho Han, Youngsu Kwon:
2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform. ICEIC 2023: 1-3 - [c36]Sujin Park, Young-Deuk Jeon, Yi-Gyeong Kim, Min-Hyung Cho, Jinho Han, Jaehoon Chung, Jaewoong Choi, Youngsu Kwon:
DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. ISOCC 2023: 215-216 - [c35]Youngsu Kwon:
ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing. ISOCC 2023: 217-218 - [c34]Jiwon Yoon, Hyunwoo Kim, Boogyo Sim, Hyunwook Park, Yi-Gyeong Kim, Sujin Park, Youngsu Kwon, Joungho Kim:
Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect. ISOCC 2023: 247-248 - 2022
- [c33]Won Jeon, Yong Cheol Peter Cho, Hyun-Mi Kim, Hyeji Kim, Jaehoon Chung, Ju-Yeob Kim, Miyoung Lee, Chun-Gi Lyuh, Jinho Han, Youngsu Kwon:
M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. AICAS 2022: 150-153 - [c32]Hyunjeong Kwon, Hyun-Mi Kim, Chun-Gi Lyuh, Jin-Kyu Kim, Jinho Han, Youngsu Kwon:
AIWareK: Compiling PyTorch Model for AI Processor Using MLIR Framework. AICAS 2022: 463-465 - [c31]Jinho Han, Chun-Gi Lyuh, Kyeongsun Shin, Hyun-Mi Kim, Hyunjeong Kwon, Jaehoon Chung, Yong Cheol Peter Cho, Jinkyu Kim, Jeonghui Suk, Chan Kim, Minseok Choi, Youngsu Kwon:
ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System. AICAS 2022: 466-468 - [c30]Hyunjeong Kwon, Youngsu Kwon, Jinho Han:
Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators. ISOCC 2022: 91-92 - 2021
- [c29]Je-Seok Ham, Yong Cheol Peter Cho, Ju-Yeob Kim, Chun-Gi Lyuh, Jin-Kyu Kim, Jinho Han, Youngsu Kwon:
HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP. HPC Asia 2021: 139-143 - [c28]Hyeji Kim, Jaehoon Chung, Kyoung-Seon Shin, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Yong Cheol Peter Cho, Jeongmin Yang, Je-Seok Ham, Minseok Choi, Jinho Han, Youngsu Kwon:
Live Demonstration: A Neural Processor for AI Acceleration. ISCAS 2021: 1
2010 – 2019
- 2019
- [c27]Youngsu Kwon, Jeongmin Yang, Yong Cheol Peter Cho, Kyoung-Seon Shin, Jaehoon Chung, Jinho Han, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Min-Seok Choi:
Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture. AICAS 2019: 127-131 - [c26]Chan Kim, In San Jeon, Young-Su Kwon, Hyun-Mi Kim, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Min-Seok Choi:
Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. ICCE-Berlin 2019: 242-247 - [c25]Youngsu Kwon, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Chan Kim, Chun-Gi Lyuh, Hyun-Mi Kim, In San Jeon, Min-Seok Choi:
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. ISOCC 2019: 174-175 - 2017
- [c24]Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, Hoi-Jun Yoo:
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. A-SSCC 2017: 313-316 - [c23]Chan Kim, Yong Cheol Peter Cho, Youngsu Kwon:
A deep learning convolution architecture for simple embedded applications. ICCE-Berlin 2017: 74-78 - 2016
- [j9]Jinho Han
, Youngsu Kwon, Kyeongjin Byun, Hoi-Jun Yoo:
A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1146-1150 (2016) - [c22]Jinho Han, Youngsu Kwon, Kyeongjin Byun, Hoi-Jun Yoo:
A fault tolerant cache system of automotive vision processor complying with ISO26262. ISCAS 2016: 2912 - 2010
- [j8]Young-Su Kwon, Nak-Woong Eum:
Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor. J. Circuits Syst. Comput. 19(7): 1435-1447 (2010) - [j7]Young-Su Kwon, Nak-Woong Eum:
Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor. Microprocess. Microsystems 34(1): 1-13 (2010) - [c21]Young-Su Kwon, Jaehyun Jang, Hyunwoo Lee, Haewook Lee, Bummo Koo, Wuk Kim, Hyeonsang Eom:
Transparent session transfer in converged IP Messaging systems. WTS 2010: 1-8
2000 – 2009
- 2009
- [c20]Young-Su Kwon, Bontae Koo, Nak-Woong Eum:
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor. ASP-DAC 2009: 329-334 - [c19]Kyungjin Byun, Young-Su Kwon, Bontae Koo, Nak-Woong Eum, Koang-Hui Jeong, Jae-Eul Koo:
Implmentation of digital audio effect SoC. ICME 2009: 1194-1197 - 2008
- [c18]Joohyun Lee, Sungdo Kim, Jinkyu Kim, Duckhwan Kim, Young-Su Kwon, Minseok Choi, Kihyuk Park, Bontae Koo, Nak-Woong Eum, Hyuckjae Lee:
A 159.2mW SoC implementation of T-DMB receiver including stacked memories. CICC 2008: 679-682 - [c17]Young-Su Kwon, Bontae Koo, Nak-Woong Eum:
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. FPL 2008: 209-214 - [c16]Young-Su Kwon, Jeong-Hum Lee, Sang-Ho Moon, Byung-Ki Kwon, Chang-Ho Choi, Jul-Ki Seok:
Standstill Parameter Identification of Vector-Controlled Induction Motor Using Frequency Characteristics of Rotor Bars. IAS 2008: 1-7 - 2005
- [j6]Young-Su Kwon, Chong-Min Kyung:
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1444-1456 (2005) - [j5]Young-Su Kwon, C.-M. Kyung:
ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 861-864 (2005) - [c15]Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ASP-DAC 2005: 499-502 - [c14]Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel:
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. SLIP 2005: 65-72 - 2004
- [j4]Young-Su Kwon, Chong-Min Kyung:
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. Microprocess. Microsystems 28(5-6): 341-350 (2004) - [c13]Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung:
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. ASP-DAC 2004: 806-811 - [c12]Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. DAC 2004: 45-48 - [c11]Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung:
Communication-efficient hardware acceleration for fast functional simulation. DAC 2004: 293-298 - [c10]Young-Su Kwon, Chong-Min Kyung:
Functional Coverage Metric Generation from Temporal Event Relation Graph. DATE 2004: 670-671 - 2003
- [c9]Young-Su Kwon, Bong-Il Park, Chong-Min Kyung:
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. ICCD 2003: 419-425 - [c8]Young-Su Kwon, Woo-Seung Yang, Chong-Min Kyung:
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. VLSI-SOC 2003: 123-128 - 2000
- [j3]Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: an application-specific programmable DSP development system. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 173-183 (2000) - [c7]Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung:
Fast development of source-level debugging system using hardware emulation (short paper). ASP-DAC 2000: 401-404 - [c6]Young-Su Kwon, In-Cheol Park, Chong-Min Kyung:
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. ASP-DAC 2000: 559-564 - [c5]Sang-Joon Nam, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, Chong-Min Kyung:
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit. CICC 2000: 551-554 - [c4]Young-Su Kwon, In-Cheol Park, Chong-Min Kyung:
Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. ICIP 2000: 191-194
1990 – 1999
- 1999
- [j2]Byoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung:
MDSP-II: a 16-bit DSP with mobile communication accelerator. IEEE J. Solid State Circuits 34(3): 397-404 (1999) - [j1]Sang-Joon Nam, Young-Su Kwon, Yeon-Ho Im, Kyung-Ku Kang, Chong-Min Kyung:
DIVA: dual-issue VLIW architecture with media instructions for image processing. IEEE Trans. Consumer Electron. 45(1): 192-202 (1999) - [c3]Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
A New Single-Clock Flip-Clop for Half-Swing Clocking. ASP-DAC 1999: 117-120 - 1998
- [c2]Byoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung:
MDSP-II: 16-bit DSP with mobile communication accelerator. CICC 1998: 5-8 - [c1]Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: An Application Specific DSP Development System. DAC 1998: 800-803
Coauthor Index
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