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ORCIDShinichiro Shiratake
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2020 – today
- 2021
[c10]Eric Karl, Shinichiro Shiratake, Jonathan Chang:
Session 24 Overview: Advanced Embedded Memories Memory Subcommittee. ISSCC 2021: 332-333- [c9]Yasuhiko Taito, Violante Moschiano, Shinichiro Shiratake:
Session 30 Overview: Non-Volatile Memories Memory Subcommittee. ISSCC 2021: 420-421 - [c8]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538
2010 – 2019
- 2018
- [c7]Shinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata:
Session 30 overview: Emerging memories: Memory and technology directions subcommittees. ISSCC 2018: 476-477 - [c6]Vivek De, Dennis Sylvester, James Myers, Jun Deguchi, Shinichiro Shiratake, Ingrid Verbauwhede
:
F1: Intelligent energy-efficient systems at the edge of IoT. ISSCC 2018: 502-504 - 2017
- [c5]Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst:
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. ISSCC 2017: 506-508 - 2015
- [j7]Ryu Ogiwara, Daisaburo Takashima, Sumiko M. Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga:
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. IEEE J. Solid State Circuits 50(5): 1324-1331 (2015) - 2011
- [j6]Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE J. Solid State Circuits 46(9): 2171-2179 (2011) - 2010
- [j5]Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. IEEE J. Solid State Circuits 45(1): 142-152 (2010) - [j4]Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1745-1752 (2010) - [c4]Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. ISSCC 2010: 262-263
2000 – 2009
- 2009
- [c3]Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC 2009: 464-465 - 2006
- [j3]Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi:
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Trans. Electron. 89-C(3): 263-270 (2006) - [j2]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006) - [c2]Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami:
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. ASP-DAC 2006: 533-540 - [c1]Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. ISSCC 2006: 459-466 - 2003
- [j1]Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr:
A 32-Mb chain FeRAM with segment/stitch array architecture. IEEE J. Solid State Circuits 38(11): 1911-1919 (2003)
Coauthor Index
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