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ORCIDNaresh R. Shanbhag
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- affiliation: University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, IL, USA
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2020 – today
- 2025
[j91]Saion K. Roy
, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag:
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation. IEEE J. Solid State Circuits 60(3): 1092-1102 (2025)- 2024
- [j90]Hyungyo Kim, Naresh R. Shanbhag:
Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection. IEEE Trans. Signal Process. 72: 2799-2811 (2024) - [c142]Saion K. Roy, Naresh R. Shanbhag:
On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. ICCAD 2024: 166:1-166:9 - 2023
- [c141]Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo:
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. DATE 2023: 1-6 - [c140]Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag:
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. ESSCIRC 2023: 25-28 - [c139]Hyungyo Kim, Naresh R. Shanbhag:
Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method. ICASSP 2023: 1-5 - [c138]Han-Mo Ou, Naresh R. Shanbhag:
Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing. ICASSP 2023: 1-5 - [c137]Hassan Dbouk, Naresh R. Shanbhag:
On the Robustness of Randomized Ensembles to Adversarial Perturbations. ICML 2023: 7303-7328 - [i18]Hassan Dbouk, Naresh R. Shanbhag:
On the Robustness of Randomized Ensembles to Adversarial Perturbations. CoRR abs/2302.01375 (2023) - 2022
- [j89]Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3188-3201 (2022) - [c136]Naresh R. Shanbhag, Saion K. Roy:
Comprehending In-memory Computing Trends via Proper Benchmarking. CICC 2022: 1-7 - [c135]Sujan Kumar Gonugondla, Naresh R. Shanbhag:
IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment. ICASSP 2022: 66-70 - [c134]Hassan Dbouk, Naresh R. Shanbhag:
Adversarial Vulnerability of Randomized Ensembles. ICML 2022: 4890-4917 - [c133]Saion K. Roy, Ameya Patil, Naresh R. Shanbhag:
Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures. ISCAS 2022: 384-388 - [i17]Hassan Dbouk, Naresh R. Shanbhag:
Adversarial Vulnerability of Randomized Ensembles. CoRR abs/2206.06737 (2022) - [i16]Klara Nahrstedt, Naresh R. Shanbhag, Vikram S. Adve, Nancy M. Amato, Romit Roy Choudhury, Carl A. Gunter, Nam Sung Kim, Olgica Milenkovic, Sayan Mitra, Lav R. Varshney, Yurii Vlasov, Sarita V. Adve, Rashid Bashir, Andreas Cangellaris, James DiCarlo, Katie Driggs-Campbell, Nick Feamster, Mattia Gazzola, Karrie Karahalios, Sanmi Koyejo, Paul G. Kwiat, Bo Li, Negar Mehr, Ravish Mehra, Andrew Miller, Daniela Rus, Alexander G. Schwing, Anshumali Shrivastava:
Coordinated Science Laboratory 70th Anniversary Symposium: The Future of Computing. CoRR abs/2210.08974 (2022) - 2021
- [j88]Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag:
A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. IEEE J. Solid State Circuits 56(7): 2234-2244 (2021) - [j87]Charbel Sakr, Naresh R. Shanbhag:
Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures. IEEE Trans. Signal Process. 69: 6462-6472 (2021) - [c132]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c131]Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler:
Optimizing Selective Protection for CNN Resilience. ISSRE 2021: 127-138 - [c130]Hassan Dbouk, Naresh R. Shanbhag:
Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. NeurIPS 2021: 12027-12039 - [i15]Ameya D. Patil, Michael Tuttle, Alexander G. Schwing, Naresh R. Shanbhag:
Robustifying 𝓁∞ Adversarial Training to the Union of Perturbation Models. CoRR abs/2105.14710 (2021) - [i14]Hassan Dbouk, Naresh R. Shanbhag:
Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. CoRR abs/2110.14871 (2021) - 2020
- [j86]Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag:
Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing. Proc. IEEE 108(12): 2251-2275 (2020) - [j85]Mingu Kang, Yongjune Kim, Ameya D. Patil, Naresh R. Shanbhag:
Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1627-1639 (2020) - [c129]Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag:
KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting. CICC 2020: 1-4 - [c128]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) 2020: 90-106 - [c127]Hassan Dbouk, Hanfei Geng, Craig M. Vineyard, Naresh R. Shanbhag:
Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition. ICASSP 2020: 1598-1602 - [c126]Sujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag:
SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. ICCAD 2020: 93:1-93:9 - [c125]Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on the Precision of In-memory Architectures. ICCAD 2020: 128:1-128:9 - [i13]Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler:
HarDNN: Feature Map Vulnerability Evaluation in CNNs. CoRR abs/2002.09786 (2020) - [i12]Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong:
Nanotechnology-inspired Information Processing Systems of the Future. CoRR abs/2005.02434 (2020) - [i11]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR abs/2007.09818 (2020) - [i10]Sujan Kumar Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications. CoRR abs/2012.13645 (2020)
2010 – 2019
- 2019
- [j84]Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
Minimum Precision Requirements of General Margin Hyperplane Classifiers. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 253-266 (2019) - [j83]Yongjune Kim, Ravi Kiran Raman, Young-Sik Kim, Lav R. Varshney, Naresh R. Shanbhag:
Efficient Local Secret Sharing for Distributed Blockchain Systems. IEEE Commun. Lett. 23(2): 282-285 (2019) - [j82]Mingu Kang, Prakalp Srivastava, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag:
An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms. IEEE Micro 39(5): 64-72 (2019) - [j81]Naresh R. Shanbhag, Naveen Verma, Yongjune Kim, Ameya D. Patil, Lav R. Varshney:
Shannon-Inspired Statistical Computing for the Nanoscale Era. Proc. IEEE 107(1): 90-107 (2019) - [c124]Charbel Sakr, Naresh R. Shanbhag:
Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. ICLR (Poster) 2019 - [c123]Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan:
Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. ICLR (Poster) 2019 - [c122]Ameya D. Patil, Haocheng Hua, Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag:
An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks. ISCAS 2019: 1-5 - [c121]Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag:
An Energy-Efficient Classifier via Boosted Spin Channel Networks. ISCAS 2019: 1-5 - [i9]Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan:
Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. CoRR abs/1901.06588 (2019) - 2018
- [j80]Mingu Kang, Sungmin Lim, Sujan K. Gonugondla, Naresh R. Shanbhag:
An In-Memory VLSI Architecture for Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 494-505 (2018) - [j79]Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag:
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. IEEE J. Solid State Circuits 53(2): 642-655 (2018) - [j78]Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Naresh R. Shanbhag:
A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator. IEEE J. Solid State Circuits 53(7): 2126-2135 (2018) - [j77]Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag:
A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training. IEEE J. Solid State Circuits 53(11): 3163-3173 (2018) - [j76]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs. IEEE Trans. Commun. 66(10): 4826-4841 (2018) - [j75]Yingyan Lin, Sai Zhang, Naresh R. Shanbhag:
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime. J. Signal Process. Syst. 90(10): 1439-1451 (2018) - [c120]Charbel Sakr, Naresh R. Shanbhag:
Minimum Precision Requirements for Deep Learning with Biomedical Datasets. BioCAS 2018: 1-4 - [c119]Charbel Sakr, Naresh R. Shanbhag:
An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks. ICASSP 2018: 1090-1094 - [c118]Charbel Sakr, Jungwook Choi, Zhuo Wang, Kailash Gopalakrishnan, Naresh R. Shanbhag:
True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization. ICASSP 2018: 2346-2350 - [c117]Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag:
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. ISCA 2018: 43-56 - [c116]Sujan K. Gonugondla, Mingu Kang, Yongjune Kim, Mark Helm, Sean Eilert, Naresh R. Shanbhag:
Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. ISCAS 2018: 1-5 - [c115]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
SRAM Bit-line Swings Optimization using Generalized Waterfilling. ISIT 2018: 1670-1674 - [c114]Sujan Kumar Gonugondla, Mingu Kang, Naresh R. Shanbhag:
A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. ISSCC 2018: 490-492 - [i8]Charbel Sakr, Naresh R. Shanbhag:
Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. CoRR abs/1812.11732 (2018) - 2017
- [j74]Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag:
Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers. IEEE Trans. Commun. 65(3): 1234-1246 (2017) - [c113]Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC 2017: 18:1-18:2 - [c112]Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag:
A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array. ESSCIRC 2017: 263-266 - [c111]Charbel Sakr, Ameya D. Patil, Sai Zhang, Yongjune Kim, Naresh R. Shanbhag:
Minimum precision requirements for the SVM-SGD learning algorithm. ICASSP 2017: 1138-1142 - [c110]Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
Analytical Guarantees on Numerical Precision of Deep Neural Networks. ICML 2017: 3007-3016 - [c109]Yingyan Lin, Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
PredictiveNet: An energy-efficient convolutional neural network via zero prediction. ISCAS 2017: 1-4 - [i7]Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag:
Shannon-inspired Statistical Computing to Enable Spintronics. CoRR abs/1702.06119 (2017) - [i6]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
Generalized Water-filling for Source-Aware Energy-Efficient SRAMs. CoRR abs/1710.07153 (2017) - 2016
- [j73]Rami A. Abdallah, Naresh R. Shanbhag:
Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation". IEEE J. Solid State Circuits 51(6): 1499 (2016) - [j72]Mingu Kang, Naresh R. Shanbhag:
In-Memory Computing Architectures for Sparse Distributed Memory. IEEE Trans. Biomed. Circuits Syst. 10(4): 855-863 (2016) - [j71]Yingyan Lin, Min-Sun Keel, Adam C. Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, Andrew C. Singer:
A Study of BER-Optimal ADC-Based Receiver for Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 693-704 (2016) - [j70]Sai Zhang, Naresh R. Shanbhag:
Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition. IEEE Trans. Signal Process. 64(13): 3338-3350 (2016) - [j69]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 897-908 (2016) - [c108]Sai Zhang, Naresh R. Shanbhag:
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. DATE 2016: 481-486 - [c107]Sujan K. Gonugondla, Byonghyo Shim, Naresh R. Shanbhag:
Perfect error compensation via algorithmic error cancellation. ICASSP 2016: 966-970 - [c106]Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag:
Analysis of error resiliency of belief propagation in computer vision. ICASSP 2016: 1060-1064 - [c105]Yingyan Lin, Sai Zhang, Naresh R. Shanbhag:
Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime. SiPS 2016: 17-22 - [i5]Sai Zhang, Mingu Kang, Charbel Sakr, Naresh R. Shanbhag:
Reducing the Energy Cost of Inference via In-sensor Information Processing. CoRR abs/1607.00667 (2016) - [i4]Charbel Sakr, Ameya Patil, Sai Zhang, Naresh R. Shanbhag:
Understanding the Energy and Precision Requirements for Online Learning. CoRR abs/1607.00669 (2016) - [i3]Sai Zhang, Naresh R. Shanbhag:
Error-Resilient Machine Learning in Near Threshold Voltage via Classifier Ensemble. CoRR abs/1607.07804 (2016) - [i2]Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag:
A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array. CoRR abs/1610.07501 (2016) - [i1]Naresh R. Shanbhag:
Energy-efficient Machine Learning in Silicon: A Communications-inspired Approach. CoRR abs/1611.03109 (2016) - 2015
- [j68]Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 598-602 (2015) - [c104]Mingu Kang, Sujan K. Gonugondla, Min-Sun Keel, Naresh R. Shanbhag:
An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. ICASSP 2015: 1037-1041 - [c103]Sai Zhang, Naresh R. Shanbhag:
Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. ICCAD 2015: 15-21 - [c102]Mingu Kang, Eric P. Kim, Min-Sun Keel, Naresh R. Shanbhag:
Energy-efficient and high throughput sparse distributed memory architecture. ISCAS 2015: 2505-2508 - [c101]Naresh R. Shanbhag:
Statistical information processing: Computing for the nanoscale era. ISLPED 2015: 1 - 2014
- [j67]Sai Zhang, Jane S. Tu, Naresh R. Shanbhag, Philip T. Krein:
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. IEEE J. Solid State Circuits 49(11): 2644-2657 (2014) - [j66]Sai Zhang, Naresh R. Shanbhag, Philip T. Krein:
System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 726-730 (2014) - [j65]Rami A. Abdallah, Naresh R. Shanbhag:
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1328-1337 (2014) - [c100]Sai Zhang, Naresh R. Shanbhag:
Embedded error compensation for energy efficient DSP systems. GlobalSIP 2014: 30-34 - [c99]Eric P. Kim, Naresh R. Shanbhag:
Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation. GlobalSIP 2014: 55-59 - [c98]Mingu Kong, Min-Sun Keel, Naresh R. Shanbhag, Sean Eilert, Ken Curewitz:
An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM. ICASSP 2014: 8326-8330 - [c97]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
A robust message passing based stereo matching kernel via system-level error resiliency. ICASSP 2014: 8331-8335 - [c96]Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag:
Space-time slicer architectures for analog-to-information conversion in channel equalizers. ICC 2014: 2124-2129 - [c95]Ihab Nahlus, Eric P. Kim, Naresh R. Shanbhag, David T. Blaauw:
Energy-efficient dot product computation using a switched analog circuit architecture. ISLPED 2014: 315-318 - 2013
- [j64]Rami A. Abdallah, Naresh R. Shanbhag:
An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation. IEEE J. Solid State Circuits 48(11): 2882-2893 (2013) - [j63]Rami A. Abdallah, Naresh R. Shanbhag:
Robust and Energy Efficient Multimedia Systems via Likelihood Processing. IEEE Trans. Multim. 15(2): 257-267 (2013) - [c94]Eric P. Kim, Naresh R. Shanbhag:
Statistical analysis of algorithmic noise tolerance. ICASSP 2013: 2731-2735 - [c93]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient systems via statistical signal processing. SiPS 2013: 312-317 - [c92]Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag:
Error resilient MRF message passing architecture for stereo matching. SiPS 2013: 348-353 - [p2]Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae:
Signal Processing for High-Speed Links. Handbook of Signal Processing Systems 2013: 315-348 - 2012
- [j62]Eric P. Kim, Naresh R. Shanbhag:
Soft N-Modular Redundancy. IEEE Trans. Computers 61(3): 323-336 (2012) - [j61]Rajan Narasimha, Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer:
BER-Optimal Analog-to-Digital Converters for Communication Links. IEEE Trans. Signal Process. 60(7): 3683-3691 (2012) - [c91]Peter Kairouz, Aolin Xu, Naresh R. Shanbhag, Andrew C. Singer:
A sphere decoding approach for the vector Viterbi algorithm. ACSCC 2012: 114-118 - [c90]Rami A. Abdallah, Naresh R. Shanbhag:
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. CICC 2012: 1-4 - [c89]Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag:
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. CICC 2012: 1-4 - [c88]Rajan Narasimha, Georg Zeitler, Naresh R. Shanbhag, Andrew C. Singer, Gerhard Kramer:
System-driven metrics for the design and adaptation of analog to digital converters. ICASSP 2012: 5281-5284 - [c87]Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag:
A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. ICASSP 2012: 5289-5292 - [c86]Eric P. Kim, Naresh R. Shanbhag:
Energy-Efficient LDPC Decoders Based on Error-Resiliency. SiPS 2012: 149-154 - [e2]Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera:
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, ISBN 978-1-4503-1249-3 [contents] - 2011
- [j60]Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag:
VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Inf. Theory 57(2): 648-667 (2011) - [c85]Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag:
Low power and error resilient PN code acquisition filter via statistical error compensation. CICC 2011: 1-4 - [c84]Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag:
Timing error statistics for energy-efficient robust DSP systems. DATE 2011: 285-288 - [c83]Naresh R. Shanbhag, Andrew C. Singer:
System-assisted analog mixed-signal design. DATE 2011: 1491-1496 - [c82]Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag:
Least squares approximation and polyphase decomposition for pipelining recursive filters. ICASSP 2011: 1661-1664 - [c81]Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein:
System energy minimization via joint optimization of the DC-DC converter and the core. ISLPED 2011: 97-102 - [c80]Eric P. Kim, Naresh R. Shanbhag:
An energy-efficient multiple-input multiple-output (MIMO) detector architecture. SiPS 2011: 239-244 - 2010
- [j59]Rami A. Abdallah, Naresh R. Shanbhag:
Minimum-Energy Operation Via Error Resiliency. IEEE Embed. Syst. Lett. 2(4): 115-118 (2010) - [j58]Rajan Narasimha, Naresh R. Shanbhag:
Design of Energy-Efficient High-Speed Links via Forward Error Correction. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 359-363 (2010) - [j57]Sriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag:
Computation as estimation: a general framework for robustness and energy efficiency in SoCs. IEEE Trans. Signal Process. 58(8): 4416-4421 (2010) - [j56]Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Stochastic Networked Computation. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1421-1432 (2010) - [c79]Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones:
Stochastic computation. DAC 2010: 859-864 - [c78]Eric P. Kim, Naresh R. Shanbhag:
Soft NMR: Analysis & application to DSP systems. ICASSP 2010: 1494-1497 - [c77]Rami A. Abdallah, Naresh R. Shanbhag:
Robust and energy-efficient DSP systems via output probability processing. ICCD 2010: 38-44 - [c76]Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer:
BER-optimal analog-to-digital converters for communication links. ISCAS 2010: 1029-1032 - [c75]Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto:
Transceiver circuits for optical communications. ISSCC 2010: 514-515 - [c74]Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne:
Energy-efficient high-speed interfaces. ISSCC 2010: 524-525 - [p1]Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae:
Signal Processing for High-Speed Links. Handbook of Signal Processing Systems 2010: 69-101 - [e1]Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim:
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, ISBN 978-1-4503-0146-6 [contents]
2000 – 2009
- 2009
- [j55]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient low-power Viterbi decoder architectures. IEEE Trans. Signal Process. 57(12): 4906-4917 (2009) - [c73]Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag:
Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. GLOBECOM 2009: 1-6 - [c72]Eric P. Kim, Rami A. Abdallah, Naresh R. Shanbhag:
Soft NMR: Exploiting statistics for energy-efficiency. SoC 2009: 52-55 - [c71]Junho Cho, Naresh R. Shanbhag, Wonyong Sung:
Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. SiPS 2009: 040-045 - [c70]Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag:
Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. SiPS 2009: 185-190 - 2008
- [j54]Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey:
The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. 25(4): 334-343 (2008) - [j53]Hyeon-Min Bae, Jonathan B. Ashbrook, Naresh R. Shanbhag, Andrew C. Singer:
Fast Power Transient Management for OC-192 WDM Add/Drop Networks. IEEE J. Solid State Circuits 43(12): 2958-2966 (2008) - [j52]Andrew C. Singer, Naresh R. Shanbhag, Hyeon-Min Bae:
Electronic dispersion compensation. IEEE Signal Process. Mag. 25(6): 110-130 (2008) - [j51]Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag:
Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 314-318 (2008) - [j50]Girish Varatkar, Naresh R. Shanbhag:
Error-Resilient Motion Estimation Architecture. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1399-1412 (2008) - [c69]Rajan Lakshmi Narasimha, Naresh R. Shanbhag:
Forward error correction for high-speed I/O. ACSCC 2008: 1513-1517 - [c68]Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI 2008: 351-354 - [c67]Shrikanth S. Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag:
Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. ICASSP 2008: 1421-1424 - [c66]Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ISCAS 2008: 380-383 - [c65]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient low-power Viterbi decoders. ISLPED 2008: 111-116 - [c64]Hyeon-Min Bae, Andrew C. Singer, Jonathan B. Ashbrook, Naresh R. Shanbhag:
A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks. ISSCC 2008: 234-235 - [c63]Yuriy M. Greshishchev, Takuji Yamamoto, Naresh R. Shanbhag:
Trends and Challenges in Optical Communications Front-End. ISSCC 2008: 394-395 - [c62]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient low-power Viterbi decoders via state clustering. SiPS 2008: 221-226 - 2007
- [j49]Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 977-982 (2007) - [c61]Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Sensor Network-On-Chip. SoC 2007: 1-4 - [c60]Girish Varatkar, Naresh R. Shanbhag:
Variation-Tolerant Motion Estimation Architecture. SiPS 2007: 126-131 - 2006
- [j48]Mohammad M. Mansour, Naresh R. Shanbhag:
A 640-Mb/s 2048-bit programmable LDPC decoder chip. IEEE J. Solid State Circuits 41(3): 684-698 (2006) - [j47]Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer, Sanjiv Chopra:
An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links. IEEE J. Solid State Circuits 41(11): 2541-2554 (2006) - [j46]Ming Zhang, Naresh R. Shanbhag:
Soft-Error-Rate-Analysis (SERA) Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2140-2155 (2006) - [j45]Ming Zhang, Naresh R. Shanbhag:
Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance. IEEE Trans. Circuits Syst. II Express Briefs 53-II(12): 1461-1465 (2006) - [j44]Byonghyo Shim, Naresh R. Shanbhag:
Energy-efficient soft error-tolerant digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 336-348 (2006) - [j43]Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel:
Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1368-1378 (2006) - [c59]Girish Varatkar, Naresh R. Shanbhag:
Energy-efficient motion estimation using error-tolerance. ISLPED 2006: 113-118 - [c58]Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer, Sanjiv Chopra:
An MLSE receiver for electronic-dispersion compensation of OC-192 fiber links. ISSCC 2006: 874-883 - 2005
- [j42]James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney:
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. IEEE J. Solid State Circuits 40(1): 80-88 (2005) - [j41]Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
A 285-MHz pipelined MAP decoder in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(8): 1718-1725 (2005) - [j40]Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag:
Linear turbo equalization analysis via BER transfer and EXIT charts. IEEE Trans. Signal Process. 53(8-1): 2883-2897 (2005) - [j39]Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for system-on-chip networks: a unified framework. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 655-667 (2005) - [j38]Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
Area-efficient high-throughput MAP decoder architectures. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 921-933 (2005) - [j37]Naresh R. Shanbhag, Keshab K. Parhi:
Guest Editorial. J. VLSI Signal Process. 39(1-2): 5-6 (2005) - [j36]Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
Energy Efficient VLSI Architecture for Linear Turbo Equalizer. J. VLSI Signal Process. 39(1-2): 49-62 (2005) - [j35]Mohammad M. Mansour, Naresh R. Shanbhag:
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. J. VLSI Signal Process. 40(3): 371-382 (2005) - [c57]Ming Zhang, Naresh R. Shanbhag:
An energy-efficient circuit technique for single event transient noise-tolerance. ISCAS (1) 2005: 636-639 - [c56]Srinivasa R. Sridhara, Naresh R. Shanbhag:
A low-power bus design using joint repeater insertion and coding. ISLPED 2005: 99-102 - [c55]Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan:
Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647 - [c54]Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design 2005: 417-422 - 2004
- [j34]Naresh R. Shanbhag:
Reliable and Efficient System-on-Chip Design. Computer 37(3): 42-50 (2004) - [j33]Rajamohana Hegde, Naresh R. Shanbhag:
A voltage overscaled low-power digital filter IC. IEEE J. Solid State Circuits 39(2): 388-391 (2004) - [j32]Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag:
Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 497-510 (2004) - [c53]Naresh R. Shanbhag:
A communication-theoretic design paradigm for reliable SOCs. DAC 2004: 76 - [c52]Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for system-on-chip networks: a unified framework. DAC 2004: 103-106 - [c51]Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag:
Switching LMS linear turbo equalization. ICASSP (4) 2004: 641-644 - [c50]Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag:
VLSI architectures for soft-decision decoding of Reed-Solomon codes. ICC 2004: 2584-2590 - [c49]Ming Zhang, Naresh R. Shanbhag:
A soft error rate analysis (SERA) methodology. ICCAD 2004: 111-118 - [c48]Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag:
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD 2004: 12-17 - [c47]Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
Switching methods for linear turbo equalization. ISCAS (3) 2004: 601-604 - [c46]Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag:
Reduced complexity interpolation for soft-decoding of reed-solomon codes. ISIT 2004: 385 - 2003
- [j31]Byonghyo Shim, Naresh R. Shanbhag:
Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. IEEE Trans. Signal Process. 51(1): 282-292 (2003) - [j30]Lei Wang, Naresh R. Shanbhag:
Low-power filtering via adaptive error-cancellation. IEEE Trans. Signal Process. 51(2): 575-583 (2003) - [j29]Lei Wang, Naresh R. Shanbhag:
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 254-269 (2003) - [j28]Lei Wang, Naresh R. Shanbhag:
Low-power MIMO signal processing. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 434-445 (2003) - [j27]Mohammad M. Mansour, Naresh R. Shanbhag:
VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 627-650 (2003) - [j26]Mohammad M. Mansour, Naresh R. Shanbhag:
High-throughput LDPC decoders. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 976-996 (2003) - [c45]Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag:
Analysis of linear turbo equalizer via EXIT chart. GLOBECOM 2003: 2237-2242 - [c44]Ganesh Balamurugan, Naresh R. Shanbhag:
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD 2003: 254-260 - [c43]Mohammad M. Mansour, Naresh R. Shanbhag:
Architecture-aware low-density parity-check codes. ISCAS (2) 2003: 57-60 - [c42]Byonghyo Shim, Naresh R. Shanbhag:
Performance analysis of algorithmic noise-tolerance techniques. ISCAS (4) 2003: 113-116 - [c41]Hyeon-Min Bae, Naresh R. Shanbhag:
High bandwidth transimpedance amplifier design using active transmission lines. ISCAS (1) 2003: 253-256 - [c40]Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
A low-power VLSI architecture for turbo decoding. ISLPED 2003: 366-371 - 2002
- [j25]Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits 37(5): 624-632 (2002) - [c39]Naresh R. Shanbhag:
Reliable and energy-efficient digital signal processing. DAC 2002: 830-835 - [c38]Mohammad M. Mansour, Naresh R. Shanbhag:
Turbo decoder architectures for low-density parity-check codes. GLOBECOM 2002: 1383-1388 - [c37]Mohammad M. Mansour, Naresh R. Shanbhag:
Design methodology for high-speed iterative decoder architectures. ICASSP 2002: 3085-3088 - [c36]Mohammad M. Mansour, Naresh R. Shanbhag:
Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) 2002: 109-112 - [c35]Mohammad M. Mansour, Naresh R. Shanbhag:
Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289 - 2001
- [j24]Ganesh Balamurugan, Naresh R. Shanbhag:
The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid State Circuits 36(2): 273-280 (2001) - [j23]Dilip V. Sarwate, Naresh R. Shanbhag:
High-speed architectures for Reed-Solomon decoders. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 641-655 (2001) - [j22]Rajamohana Hegde, Naresh R. Shanbhag:
Soft digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 813-823 (2001) - [j21]Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran:
Total System Energy Minimization for Wireless Image Transmission. J. VLSI Signal Process. 27(1-2): 99-117 (2001) - [j20]Wayne P. Burleson, Naresh R. Shanbhag:
Guest Editorial: Reconfigurable Signal Processing Systems. J. VLSI Signal Process. 28(1-2): 5-6 (2001) - [c34]Jonathan B. Ashbrook, Naresh R. Shanbhag, Ralf Koetter, Richard E. Blahut:
Implementation of a Hermitian decoder IC in 0.35 μm CMOS. CICC 2001: 297-300 - [c33]Rajamohana Hegde, Naresh R. Shanbhag:
A low-power digital filter IC via soft DSP. CICC 2001: 309-312 - [c32]Lei Wang, Naresh R. Shanbhag:
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. ISLPED 2001: 334-339 - 2000
- [j19]Rajamohana Hegde, Naresh R. Shanbhag:
Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 379-391 (2000) - [c31]Ganesh Balamurugan, Naresh R. Shanbhag:
A noise-tolerant dynamic circuit design technique. CICC 2000: 425-428 - [c30]Rajamohana Hegde, Naresh R. Shanbhag:
Algorithmic noise-tolerance for low-power signal processing in the deep submicron era. EUSIPCO 2000: 1-4 - [c29]Rajamohana Hegde, Naresh R. Shanbhag:
Low-power digital filtering via soft DSP. ICASSP 2000: 3243-3246 - [c28]Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 - [c27]Mohammad M. Mansour, Makram M. Mansour, Ibrahim N. Hajj, Naresh R. Shanbhag:
Instruction scheduling for low power on dynamically variable voltage processors. ICECS 2000: 613-618 - [c26]Dongwon Seo, Naresh R. Shanbhag, Milton Feng:
Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform. ISCAS 2000: 9-12 - [c25]Naresh R. Shanbhag, Lei Wang:
Energy-efficiency bounds for noise-tolerant dynamic circuits. ISCAS 2000: 273-276 - [c24]Manish Sharma, Naresh R. Shanbhag:
Architecture driven filter transformations. ISCAS 2000: 601-604 - [c23]Naresh R. Shanbhag, Krishnamurthy Soumyanath, Samuel Martin:
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED 2000: 295-302
1990 – 1999
- 1999
- [j18]Rajamohana Hegde, Naresh R. Shanbhag:
A low-power phase-splitting adaptive equalizer for high bit-rate communication systems. IEEE Trans. Signal Process. 47(3): 911-915 (1999) - [j17]Manish Goel, Naresh R. Shanbhag:
Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers. IEEE Trans. Signal Process. 47(10): 2821-2832 (1999) - [j16]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
A coding framework for low-power address and data busses. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 212-221 (1999) - [j15]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 359-368 (1999) - [j14]Manish Goel, Naresh R. Shanbhag:
Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 463-476 (1999) - [c22]Manish Goel, Naresh R. Shanbhag:
Low-power channel coding via dynamic reconfiguration. ICASSP 1999: 1893-1896 - [c21]Rajamohana Hegde, Naresh R. Shanbhag:
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) 1999: 334-337 - [c20]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) 1999: 470-473 - [c19]Lei Wang, Naresh R. Shanbhag:
Noise-tolerant dynamic circuit design. ISCAS (1) 1999: 549-552 - [c18]Ganesh Balamurugan, Naresh R. Shanbhag:
Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED 1999: 24-29 - [c17]Rajamohana Hegde, Naresh R. Shanbhag:
Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED 1999: 30-35 - [c16]Jayanto Minocha, Naresh R. Shanbhag:
A low power data-adaptive motion estimation algorithm. MMSP 1999: 685-690 - [c15]Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag:
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design 1999: 358- - 1998
- [j13]Naresh R. Shanbhag:
Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design. Int. J. Wirel. Inf. Networks 5(2): 147-171 (1998) - [j12]Naresh R. Shanbhag, Gi-Hong Im:
VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access. IEEE Trans. Signal Process. 46(5): 1403-1416 (1998) - [j11]Manish Goel, Naresh R. Shanbhag:
Finite-precision analysis of the pipelined strength-reduced adaptive filter. IEEE Trans. Signal Process. 46(6): 1763-1769 (1998) - [j10]Gi-Hong Im, Naresh R. Shanbhag:
A pipelined adaptive NEXT canceller. IEEE Trans. Signal Process. 46(8): 2252-2258 (1998) - [c14]Manoj Aggarwal, Naresh R. Shanbhag, Narendra Ahuja:
Improving the throughput of flexible-precision DSPS via algorithm transformation. ICASSP 1998: 3069-3072 - [c13]Manish Goel, Naresh R. Shanbhag:
Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT). ICASSP 1998: 3081-3084 - [c12]Rajamohana Hegde, Naresh R. Shanbhag:
Energy-efficiency in presence of deep submicron noise. ICCAD 1998: 228-234 - [c11]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED 1998: 250-255 - [c10]Swaroop Appadwedula, Manish Goel, Douglas L. Jones, Kannan Ramchandran, Naresh R. Shanbhag:
Efficient wireless image transmission under a total power constraint. MMSP 1998: 573-578 - [c9]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design 1998: 18-23 - 1997
- [j9]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 718-733 (1997) - [j8]Naresh R. Shanbhag, Manish Goel:
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN. IEEE Trans. Signal Process. 45(5): 1276-1290 (1997) - [c8]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC 1997: 582-587 - [c7]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Achievable bounds on signal transition activity. ICCAD 1997: 126-129 - [c6]Manish Goel, Naresh R. Shanbhag:
Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. ISLPED 1997: 161-166 - 1996
- [j7]Naresh R. Shanbhag, Gi-Hong Im:
Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations. IEEE Trans. Signal Process. 44(7): 1841-1847 (1996) - [c5]Naresh R. Shanbhag:
Lower bounds on power dissipation for DSP algorithms. ISLPED 1996: 43-48 - [c4]Manish Goel, Naresh R. Shanbhag:
Low-power adaptive filter architectures via strength reduction. ISLPED 1996: 217-220 - 1995
- [j6]Naresh R. Shanbhag, Keshab K. Parhi:
Pipelined adaptive DFE architectures using relaxed look-ahead. IEEE Trans. Signal Process. 43(6): 1368-1385 (1995) - [c3]Naresh R. Shanbhag, Gi-Hong Im:
Pipelined Adaptive IIR Filter Architecture. ISCAS 1995: 558-561 - 1993
- [j5]Naresh R. Shanbhag, Keshab K. Parhi:
A pipelined adaptive lattice filter architecture. IEEE Trans. Signal Process. 41(5): 1925-1939 (1993) - [c2]Naresh R. Shanbhag, Keshab K. Parhi:
Roundoff error analysis of the pipelined ADPCM coder. ISCAS 1993: 886-889 - [c1]Naresh R. Shanbhag, Keshab K. Parhi:
A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS 1993: 1956-1958 - 1991
- [j4]Naresh R. Shanbhag, Raymond E. Siferd:
A single-chip pipelined 2-D FIR filter using residue arithmetic. IEEE J. Solid State Circuits 26(5): 796-805 (1991) - [j3]Naresh R. Shanbhag:
An improved systolic architecture for 2-D digital filters. IEEE Trans. Signal Process. 39(5): 1195-1202 (1991) - 1990
- [j2]Naresh R. Shanbhag, Dipankar Nagchoudhuri, Raymond E. Siferd, Gangaikondan S. Visweswaran:
Quaternary logic circuits in 2- mu m CMOS technology. IEEE J. Solid State Circuits 25(3): 790-799 (1990)
1980 – 1989
- 1988
- [j1]Naresh R. Shanbhag, Pushkal Juneja:
Parallel implementation of a 4*4-bit multiplier using a modified Booth's algorithm. IEEE J. Solid State Circuits 23(4): 1010-1013 (1988)
Coauthor Index
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