Stop the war!Остановите войну!
for scientists:
Google
Google Scholar
Semantic Scholar
IA Scholar
CiteSeerX
ORCIDNaresh R. Shanbhag
Person information
- affiliation: University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, IL, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2021
[j85]Hassan Dbouk
, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag:
A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. IEEE J. Solid State Circuits 56(7): 2234-2244 (2021)- [j84]Charbel Sakr, Naresh R. Shanbhag:
Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures. IEEE Trans. Signal Process. 69: 6462-6472 (2021) - [c128]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c127]Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler:
Optimizing Selective Protection for CNN Resilience. ISSRE 2021: 127-138 - [c126]Hassan Dbouk, Naresh R. Shanbhag:
Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. NeurIPS 2021: 12027-12039 - [i15]Ameya D. Patil, Michael Tuttle, Alexander G. Schwing, Naresh R. Shanbhag:
Robustifying 𝓁∞ Adversarial Training to the Union of Perturbation Models. CoRR abs/2105.14710 (2021) - [i14]Hassan Dbouk, Naresh R. Shanbhag:
Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. CoRR abs/2110.14871 (2021) - 2020
- [j83]Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag:
Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing. Proc. IEEE 108(12): 2251-2275 (2020) - [j82]Mingu Kang, Yongjune Kim, Ameya D. Patil, Naresh R. Shanbhag:
Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1627-1639 (2020) - [c125]Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag:
KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting. CICC 2020: 1-4 - [c124]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) 2020: 90-106 - [c123]Hassan Dbouk, Hanfei Geng, Craig M. Vineyard, Naresh R. Shanbhag:
Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition. ICASSP 2020: 1598-1602 - [c122]Sujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag:
SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. ICCAD 2020: 93:1-93:9 - [c121]Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on the Precision of In-memory Architectures. ICCAD 2020: 128:1-128:9 - [i13]Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler:
HarDNN: Feature Map Vulnerability Evaluation in CNNs. CoRR abs/2002.09786 (2020) - [i12]Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong:
Nanotechnology-inspired Information Processing Systems of the Future. CoRR abs/2005.02434 (2020) - [i11]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR abs/2007.09818 (2020) - [i10]Sujan Kumar Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications. CoRR abs/2012.13645 (2020)
2010 – 2019
- 2019
- [j81]Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
Minimum Precision Requirements of General Margin Hyperplane Classifiers. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 253-266 (2019) - [j80]Yongjune Kim, Ravi Kiran Raman, Young-Sik Kim, Lav R. Varshney, Naresh R. Shanbhag:
Efficient Local Secret Sharing for Distributed Blockchain Systems. IEEE Commun. Lett. 23(2): 282-285 (2019) - [j79]Mingu Kang, Prakalp Srivastava, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag:
An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms. IEEE Micro 39(5): 64-72 (2019) - [j78]Naresh R. Shanbhag, Naveen Verma, Yongjune Kim, Ameya D. Patil, Lav R. Varshney:
Shannon-Inspired Statistical Computing for the Nanoscale Era. Proc. IEEE 107(1): 90-107 (2019) - [c120]Charbel Sakr, Naresh R. Shanbhag:
Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. ICLR (Poster) 2019 - [c119]Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan:
Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. ICLR (Poster) 2019 - [c118]Ameya D. Patil, Haocheng Hua, Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag:
An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks. ISCAS 2019: 1-5 - [c117]Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag:
An Energy-Efficient Classifier via Boosted Spin Channel Networks. ISCAS 2019: 1-5 - [i9]Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan:
Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. CoRR abs/1901.06588 (2019) - 2018
- [j77]Mingu Kang, Sungmin Lim, Sujan K. Gonugondla, Naresh R. Shanbhag:
An In-Memory VLSI Architecture for Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 494-505 (2018) - [j76]Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag:
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. IEEE J. Solid State Circuits 53(2): 642-655 (2018) - [j75]Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Naresh R. Shanbhag:
A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator. IEEE J. Solid State Circuits 53(7): 2126-2135 (2018) - [j74]Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag:
A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training. IEEE J. Solid State Circuits 53(11): 3163-3173 (2018) - [j73]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs. IEEE Trans. Commun. 66(10): 4826-4841 (2018) - [j72]Yingyan Lin, Sai Zhang, Naresh R. Shanbhag:
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime. J. Signal Process. Syst. 90(10): 1439-1451 (2018) - [c116]Charbel Sakr, Naresh R. Shanbhag:
Minimum Precision Requirements for Deep Learning with Biomedical Datasets. BioCAS 2018: 1-4 - [c115]Charbel Sakr, Naresh R. Shanbhag:
An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks. ICASSP 2018: 1090-1094 - [c114]Charbel Sakr, Jungwook Choi, Zhuo Wang, Kailash Gopalakrishnan, Naresh R. Shanbhag:
True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization. ICASSP 2018: 2346-2350 - [c113]Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag:
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. ISCA 2018: 43-56 - [c112]Sujan K. Gonugondla, Mingu Kang, Yongjune Kim, Mark Helm, Sean Eilert, Naresh R. Shanbhag:
Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. ISCAS 2018: 1-5 - [c111]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
SRAM Bit-line Swings Optimization using Generalized Waterfilling. ISIT 2018: 1670-1674 - [c110]Sujan Kumar Gonugondla, Mingu Kang, Naresh R. Shanbhag:
A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. ISSCC 2018: 490-492 - [i8]Charbel Sakr, Naresh R. Shanbhag:
Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. CoRR abs/1812.11732 (2018) - 2017
- [j71]Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag:
Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers. IEEE Trans. Commun. 65(3): 1234-1246 (2017) - [c109]Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC 2017: 18:1-18:2 - [c108]Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag:
A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array. ESSCIRC 2017: 263-266 - [c107]Charbel Sakr, Ameya D. Patil, Sai Zhang, Yongjune Kim, Naresh R. Shanbhag:
Minimum precision requirements for the SVM-SGD learning algorithm. ICASSP 2017: 1138-1142 - [c106]Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
Analytical Guarantees on Numerical Precision of Deep Neural Networks. ICML 2017: 3007-3016 - [c105]Yingyan Lin, Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag:
PredictiveNet: An energy-efficient convolutional neural network via zero prediction. ISCAS 2017: 1-4 - [i7]Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag:
Shannon-inspired Statistical Computing to Enable Spintronics. CoRR abs/1702.06119 (2017) - [i6]Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag:
Generalized Water-filling for Source-Aware Energy-Efficient SRAMs. CoRR abs/1710.07153 (2017) - 2016
- [j70]Rami A. Abdallah, Naresh R. Shanbhag:
Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation". IEEE J. Solid State Circuits 51(6): 1499 (2016) - [j69]Mingu Kang, Naresh R. Shanbhag:
In-Memory Computing Architectures for Sparse Distributed Memory. IEEE Trans. Biomed. Circuits Syst. 10(4): 855-863 (2016) - [j68]Yingyan Lin, Min-Sun Keel, Adam C. Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, Andrew C. Singer:
A Study of BER-Optimal ADC-Based Receiver for Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 693-704 (2016) - [j67]Sai Zhang, Naresh R. Shanbhag:
Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition. IEEE Trans. Signal Process. 64(13): 3338-3350 (2016) - [j66]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 897-908 (2016) - [c104]Sai Zhang, Naresh R. Shanbhag:
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. DATE 2016: 481-486 - [c103]Sujan K. Gonugondla, Byonghyo Shim, Naresh R. Shanbhag:
Perfect error compensation via algorithmic error cancellation. ICASSP 2016: 966-970 - [c102]Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag:
Analysis of error resiliency of belief propagation in computer vision. ICASSP 2016: 1060-1064 - [c101]Yingyan Lin, Sai Zhang, Naresh R. Shanbhag:
Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime. SiPS 2016: 17-22 - [i5]Sai Zhang, Mingu Kang, Charbel Sakr, Naresh R. Shanbhag:
Reducing the Energy Cost of Inference via In-sensor Information Processing. CoRR abs/1607.00667 (2016) - [i4]Charbel Sakr, Ameya Patil, Sai Zhang, Naresh R. Shanbhag:
Understanding the Energy and Precision Requirements for Online Learning. CoRR abs/1607.00669 (2016) - [i3]Sai Zhang, Naresh R. Shanbhag:
Error-Resilient Machine Learning in Near Threshold Voltage via Classifier Ensemble. CoRR abs/1607.07804 (2016) - [i2]Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag:
A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array. CoRR abs/1610.07501 (2016) - [i1]Naresh R. Shanbhag:
Energy-efficient Machine Learning in Silicon: A Communications-inspired Approach. CoRR abs/1611.03109 (2016) - 2015
- [j65]Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 598-602 (2015) - [c100]Mingu Kang, Sujan K. Gonugondla, Min-Sun Keel, Naresh R. Shanbhag:
An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. ICASSP 2015: 1037-1041 - [c99]Sai Zhang, Naresh R. Shanbhag:
Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. ICCAD 2015: 15-21 - [c98]Mingu Kang, Eric P. Kim, Min-Sun Keel, Naresh R. Shanbhag:
Energy-efficient and high throughput sparse distributed memory architecture. ISCAS 2015: 2505-2508 - [c97]Naresh R. Shanbhag:
Statistical information processing: Computing for the nanoscale era. ISLPED 2015: 1 - 2014
- [j64]Sai Zhang, Jane S. Tu, Naresh R. Shanbhag, Philip T. Krein:
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. IEEE J. Solid State Circuits 49(11): 2644-2657 (2014) - [j63]Sai Zhang, Naresh R. Shanbhag, Philip T. Krein:
System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 726-730 (2014) - [j62]Rami A. Abdallah, Naresh R. Shanbhag:
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1328-1337 (2014) - [c96]Sai Zhang, Naresh R. Shanbhag:
Embedded error compensation for energy efficient DSP systems. GlobalSIP 2014: 30-34 - [c95]Eric P. Kim, Naresh R. Shanbhag:
Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation. GlobalSIP 2014: 55-59 - [c94]Mingu Kong, Min-Sun Keel, Naresh R. Shanbhag, Sean Eilert, Ken Curewitz:
An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM. ICASSP 2014: 8326-8330 - [c93]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
A robust message passing based stereo matching kernel via system-level error resiliency. ICASSP 2014: 8331-8335 - [c92]Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag:
Space-time slicer architectures for analog-to-information conversion in channel equalizers. ICC 2014: 2124-2129 - [c91]Ihab Nahlus, Eric P. Kim, Naresh R. Shanbhag, David T. Blaauw:
Energy-efficient dot product computation using a switched analog circuit architecture. ISLPED 2014: 315-318 - 2013
- [j61]Rami A. Abdallah, Naresh R. Shanbhag:
An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation. IEEE J. Solid State Circuits 48(11): 2882-2893 (2013) - [j60]Rami A. Abdallah, Naresh R. Shanbhag:
Robust and Energy Efficient Multimedia Systems via Likelihood Processing. IEEE Trans. Multim. 15(2): 257-267 (2013) - [c90]Eric P. Kim, Naresh R. Shanbhag:
Statistical analysis of algorithmic noise tolerance. ICASSP 2013: 2731-2735 - [c89]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient systems via statistical signal processing. SiPS 2013: 312-317 - [c88]Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag:
Error resilient MRF message passing architecture for stereo matching. SiPS 2013: 348-353 - [p2]Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae:
Signal Processing for High-Speed Links. Handbook of Signal Processing Systems 2013: 315-348 - 2012
- [j59]Eric P. Kim, Naresh R. Shanbhag:
Soft N-Modular Redundancy. IEEE Trans. Computers 61(3): 323-336 (2012) - [j58]Rajan Narasimha, Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer:
BER-Optimal Analog-to-Digital Converters for Communication Links. IEEE Trans. Signal Process. 60(7): 3683-3691 (2012) - [c87]Peter Kairouz, Aolin Xu, Naresh R. Shanbhag, Andrew C. Singer:
A sphere decoding approach for the vector Viterbi algorithm. ACSCC 2012: 114-118 - [c86]Rami A. Abdallah, Naresh R. Shanbhag:
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. CICC 2012: 1-4 - [c85]Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag:
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. CICC 2012: 1-4 - [c84]Rajan Narasimha, Georg Zeitler, Naresh R. Shanbhag, Andrew C. Singer, Gerhard Kramer:
System-driven metrics for the design and adaptation of analog to digital converters. ICASSP 2012: 5281-5284 - [c83]Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag:
A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. ICASSP 2012: 5289-5292 - [c82]Eric P. Kim, Naresh R. Shanbhag:
Energy-Efficient LDPC Decoders Based on Error-Resiliency. SiPS 2012: 149-154 - [e2]Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera:
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, ISBN 978-1-4503-1249-3 [contents] - 2011
- [j57]Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag:
VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Inf. Theory 57(2): 648-667 (2011) - [c81]Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag:
Low power and error resilient PN code acquisition filter via statistical error compensation. CICC 2011: 1-4 - [c80]Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag:
Timing error statistics for energy-efficient robust DSP systems. DATE 2011: 285-288 - [c79]Naresh R. Shanbhag, Andrew C. Singer:
System-assisted analog mixed-signal design. DATE 2011: 1491-1496 - [c78]Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag:
Least squares approximation and polyphase decomposition for pipelining recursive filters. ICASSP 2011: 1661-1664 - [c77]Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein:
System energy minimization via joint optimization of the DC-DC converter and the core. ISLPED 2011: 97-102 - [c76]Eric P. Kim, Naresh R. Shanbhag:
An energy-efficient multiple-input multiple-output (MIMO) detector architecture. SiPS 2011: 239-244 - 2010
- [j56]Rami A. Abdallah, Naresh R. Shanbhag:
Minimum-Energy Operation Via Error Resiliency. IEEE Embed. Syst. Lett. 2(4): 115-118 (2010) - [j55]Rajan Narasimha, Naresh R. Shanbhag:
Design of Energy-Efficient High-Speed Links via Forward Error Correction. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 359-363 (2010) - [j54]Sriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag:
Computation as estimation: a general framework for robustness and energy efficiency in SoCs. IEEE Trans. Signal Process. 58(8): 4416-4421 (2010) - [j53]Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Stochastic Networked Computation. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1421-1432 (2010) - [c75]Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones:
Stochastic computation. DAC 2010: 859-864 - [c74]Eric P. Kim, Naresh R. Shanbhag:
Soft NMR: Analysis & application to DSP systems. ICASSP 2010: 1494-1497 - [c73]Rami A. Abdallah, Naresh R. Shanbhag:
Robust and energy-efficient DSP systems via output probability processing. ICCD 2010: 38-44 - [c72]Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer:
BER-optimal analog-to-digital converters for communication links. ISCAS 2010: 1029-1032 - [c71]Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto:
Transceiver circuits for optical communications. ISSCC 2010: 514-515 - [c70]Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne:
Energy-efficient high-speed interfaces. ISSCC 2010: 524-525 - [p1]Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae:
Signal Processing for High-Speed Links. Handbook of Signal Processing Systems 2010: 69-101 - [e1]Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim:
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, ISBN 978-1-4503-0146-6 [contents]
2000 – 2009
- 2009
- [j52]Rami A. Abdallah, Naresh R. Shanbhag:
Error-resilient low-power Viterbi decoder architectures. IEEE Trans. Signal Process. 57(12): 4906-4917 (2009) - [c69]Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag:
Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. GLOBECOM 2009: 1-6 - [c68]Eric P. Kim, Rami A. Abdallah, Naresh R. Shanbhag:
Soft NMR: Exploiting statistics for energy-efficiency. SoC 2009: 52-55 - [c67]Junho Cho, Naresh R. Shanbhag, Wonyong Sung:
Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. SiPS 2009: 040-045 - [c66]Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag:
Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. SiPS 2009: 185-190 - 2008
- [j51]Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey:
The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. 25(4): 334-343 (2008) - [j50]Hyeon-Min Bae, Jonathan B. Ashbrook, Naresh R. Shanbhag, Andrew C. Singer:
Fast Power Transient Management for OC-192 WDM Add/Drop Networks. IEEE J. Solid State Circuits 43(12): 2958-2966 (2008) - [j49]Andrew C. Singer, Naresh R. Shanbhag, Hyeon-Min Bae:
Electronic dispersion compensation. IEEE Signal Process. Mag. 25(6): 110-130 (2008) - [j48]Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag:
Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 314-318 (2008) - [j47]Girish Varatkar, Naresh R. Shanbhag:
Error-Resilient Motion Estimation Architecture. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1399-1412 (2008) - [c65]Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI 2008: 351-354 - [c64]