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2020 – today
- 2024
[j47]Naoya Onizawa
, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12: 102050-102060 (2024)- [c61]R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu:
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning. MWSCAS 2024: 928-931 - 2023
- [j46]Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu:
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. IEEE Access 11: 44923-44931 (2023) - [j45]Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 108-118 (2023) - [j44]Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34(12): 10999-11005 (2023) - [c60]Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT 2023: 274-275 - [c59]Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS 2023: 1-4 - [i6]Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR abs/2302.12454 (2023) - [i5]Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu:
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR abs/2304.11839 (2023) - 2022
- [j43]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9(3): 653-674 (2022) - [c58]Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 2022: 1-4 - 2021
- [j42]Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu:
Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access 9: 62890-62898 (2021) - [j41]Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu:
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. IEEE Open J. Circuits Syst. 2: 782-791 (2021) - [j40]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 655-665 (2021) - [j39]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 67-76 (2021) - [c57]Naoya Onizawa, Takahiro Hanyu:
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. ISCAS 2021: 1-5 - [c56]Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu:
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. SiPS 2021: 1-6 - 2020
- [j38]Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8: 188004-188014 (2020) - [j37]Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu:
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7(1): 41-58 (2020) - [j36]Naoya Onizawa, Ren Arakawa, Takahiro Hanyu:
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP 7(1): 89-109 (2020) - [j35]Makoto Kato, Naoya Onizawa, Takahiro Hanyu:
Design Automation of Invertible Logic Circuit from a Standard HDL Description. FLAP 8(5): 1311-1333 (2020) - [j34]Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1541-1550 (2020) - [j33]Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2171-2181 (2020) - [j32]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu:
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2370-2382 (2020) - [c55]Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS 2020: 283-286
2010 – 2019
- 2019
- [j31]Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2263-2274 (2019) - [c54]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. ACSSC 2019: 312-316 - [c53]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS 2019: 115-116 - [c52]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS 2019: 117-118 - [c51]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS 2019: 434-437 - 2018
- [j30]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 444-453 (2018) - [j29]Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82: 46-61 (2018) - [j28]Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu:
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2696-2708 (2018) - [j27]Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90(5): 709-725 (2018) - [c50]Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. ICECS 2018: 649-650 - [c49]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS 2018: 1-5 - [c48]Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu:
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL 2018: 156-161 - 2017
- [j26]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. 100-D(8): 1592-1602 (2017) - [j25]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5(2): 151-163 (2017) - [j24]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2688-2699 (2017) - [j23]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2724-2735 (2017) - [c47]Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125 - [c46]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui:
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE 2017: 548-553 - [c45]Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC 2017: 43-46 - [c44]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP 2017: 1315-1319 - [c43]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Evaluation of Stochastic Cascaded IIR Filters. ISMVL 2017: 224-229 - [c42]Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu:
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS 2017: 309-312 - 2016
- [j22]Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross:
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 13-24 (2016) - [j21]Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26(1-2): 125-140 (2016) - [j20]Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno:
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c41]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Gammatone filter based on stochastic computation. ICASSP 2016: 1036-1040 - [c40]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL 2016: 223-228 - [c39]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI implementation of deep neural networks using integral stochastic computing. ISTC 2016: 216-220 - [c38]Naoya Onizawa, Takahiro Hanyu:
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS 2016: 1-4 - 2015
- [j19]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22(9): 1224-1228 (2015) - [j18]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 642-653 (2015) - [c37]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE 2015: 1006-1011 - [c36]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Frequency-flexible stochastic Gabor filter. DSP 2015: 458-462 - [c35]Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu:
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL 2015: 109-114 - [c34]Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu:
Scaled IIR filter based on stochastic computation. MWSCAS 2015: 1-4 - [c33]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH 2015: 39-44 - [c32]Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu:
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS 2015: 1-4 - [c31]Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
Stochastic implementation of the disparity energy model for depth perception. SiPS 2015: 1-6 - [i4]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR abs/1509.08972 (2015) - 2014
- [j17]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j16]Naoya Onizawa, Takahiro Hanyu:
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. IEICE Electron. Express 11(24): 20141017 (2014) - [j15]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [j14]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. 97-D(9): 2286-2295 (2014) - [j13]Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu:
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers 63(3): 637-649 (2014) - [j12]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 865-876 (2014) - [j11]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. 76(2): 185-194 (2014) - [j10]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks. J. Signal Process. Syst. 76(3): 235-247 (2014) - [c30]Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu:
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS 2014: 683-686 - [c29]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC 2014: 1-8 - [c28]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL 2014: 208-213 - [c27]Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL 2014: 220-225 - [c26]Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu:
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH 2014: 59-64 - [c25]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS 2014: 193-196 - [c24]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross:
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS 2014: 133-138 - [i3]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR abs/1402.0808 (2014) - 2013
- [j9]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10(7): 20130148 (2013) - [j8]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. 96-D(9): 1952-1961 (2013) - [c23]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
A low-power Content-Addressable Memory based on clustered-sparse networks. ASAP 2013: 305-308 - [c22]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC 2013: 8-15 - [c21]Naoya Onizawa, Warren J. Gross:
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. DAC 2013: 55:1-55:6 - [c20]Hooman Jarollahi, Naoya Onizawa, Warren J. Gross:
Selective decoding in associative memories based on Sparse-Clustered Networks. GlobalSIP 2013: 1270-1273 - [c19]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Reduced-complexity binary-weight-coded associative memories. ICASSP 2013: 2523-2527 - [c18]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL 2013: 254-259 - [i2]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks. CoRR abs/1302.4463 (2013) - [i1]Hooman Jarollahi, Naoya Onizawa, Warren J. Gross:
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks. CoRR abs/1308.6021 (2013) - 2012
- [j7]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(6): 1018-1029 (2012) - [c17]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu:
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC 2012: 41-48 - [c16]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Architecture and implementation of an associative memory using sparse clustered networks. ISCAS 2012: 2901-2904 - [c15]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL 2012: 13-18 - [c14]Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross:
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL 2012: 92-97 - [c13]Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110 - [c12]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS 2012: 143-148 - 2011
- [j6]Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu:
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8): 1933-1943 (2011) - [c11]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE 2011: 776-781 - [c10]Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS 2011: 2067-2070 - [c9]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL 2011: 236-241 - 2010
- [j5]Naoya Onizawa, Takahiro Hanyu:
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. IEICE Trans. Inf. Syst. 93-D(8): 2089-2099 (2010) - [j4]Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet:
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 482-489 (2010) - [c8]Naoya Onizawa, Takahiro Hanyu:
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. ISCAS 2010: 157-160 - [c7]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL 2010: 211-216 - [c6]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI (Selected papers) 2010: 17-30 - [c5]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI 2010: 357-362
2000 – 2009
- 2009
- [j3]Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet:
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Trans. Electron. 92-C(6): 867-874 (2009) - [c4]Yo Ohtake, Naoya Onizawa, Takahiro Hanyu:
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ISCAS 2009: 1000-1003 - [c3]Naoya Onizawa, Takahiro Hanyu:
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. ISMVL 2009: 36-41 - 2008
- [j2]Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu:
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Trans. Electron. 91-C(4): 581-588 (2008) - [c2]Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu:
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75 - 2006
- [j1]Naoya Onizawa, Takahiro Hanyu:
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Trans. Electron. 89-C(11): 1575-1580 (2006) - 2005
- [c1]Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu:
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143
Coauthor Index
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