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2020 – today
- 2024
[c24]Swaminathan Sankaran, Gerd Schuppener, Juan Herbsommer, Bradley Kramer, Hassan Ali, Robert Payne, Carole Rush, Baher Haroun, Nirmal Warke:
A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links. MWSCAS 2024: 1026-1032- 2023
- [c23]Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann:
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design. ISCAS 2023: 1-5 - [c22]Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan:
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter. ISSCC 2023: 70-71 - 2022
- [j12]Tolga Dinc
, Sachin Kalia, Siraj Akhtar, Baher Haroun, Benjamin Cook, Swaminathan Sankaran:
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation. IEEE J. Solid State Circuits 57(5): 1291-1299 (2022) - [j11]Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran:
A Sub-100 Fs RMSjitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference. IEEE J. Solid State Circuits 57(5): 1372-1384 (2022) - [j10]Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan:
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing. IEEE J. Solid State Circuits 57(9): 2741-2751 (2022) - 2021
- [c21]Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran:
An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process. A-SSCC 2021: 1-3 - [c20]Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan:
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing. ISSCC 2021: 80-82 - 2020
- [c19]Danielle Griffith, Ernest Ting-Ta Yen, Kaichien Tsai, Habeeb Ur Rahman Mohammed, Baher Haroun, Ali Kiaei, Ahmad Bahai:
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production. ISSCC 2020: 58-60
2010 – 2019
- 2018
- [c18]Baher Haroun:
Autonomous Vehicles Sensor Needs. ESSCIRC 2018: 3 - [c17]Baher Haroun:
Autonomous Vehicles SEnsor Needs. ESSDERC 2018: 3 - 2017
- [j9]Aritra Banerjee, Rahmi Hezar, Lei Ding, Baher Haroun:
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1977-1988 (2017) - 2015
- [j8]Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun:
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. IEEE J. Solid State Circuits 50(5): 1107-1116 (2015) - [j7]Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun:
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications. IEEE J. Solid State Circuits 50(5): 1117-1125 (2015) - 2014
- [j6]Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun:
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS. IEEE J. Solid State Circuits 49(4): 984-995 (2014) - [c16]Aritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun:
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS. ESSCIRC 2014: 467-470 - 2013
- [j5]Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun:
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 517-528 (2013) - 2012
- [c15]Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi:
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC 2012: 158-160 - [c14]Baher Haroun, Gyu-Hyeong Cho:
Session 16 overview: Switching power control techniques: Analog subcommittee. ISSCC 2012: 272-273 - [c13]Vijay Rentala, Venkatesh Srinivasan, Victoria Wang, Srinath Ramaswamy, Baher Haroun, Marco Corsi:
Low power ADC's for wireless communications. MWSCAS 2012: 694-697 - 2010
- [c12]Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha P. Chandrakasan:
A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. ISSCC 2010: 208-209 - [c11]Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, Gangadhar Burra, Gabriel Gomez:
A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS. ISSCC 2010: 304-305
2000 – 2009
- 2006
- [j4]Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert Bogdan Staszewski, Baher Haroun:
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - 2002
- [j3]Jerry (Heng-Chih) Lin, Baher Haroun:
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique. IEEE J. Solid State Circuits 37(12): 1610-1617 (2002) - [c10]Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun:
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-153
1990 – 1999
- 1995
- [c9]Baher Haroun, Behzad Sajjadi:
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. FPGA 1995: 75-81 - [c8]Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman:
Floorplanning with Datapath Optimization. ISCAS 1995: 41-44 - 1994
- [c7]Baher Haroun, Behzard Sajjadi:
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. ICCD 1994: 587-589 - [c6]Baher Haroun, Chao Hua Wu:
A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. ISCAS 1994: 9-12 - [c5]Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman:
A Floorplanner driven by Structural & Timing Constraints. ISCAS 1994: 157-160 - [c4]Reza Golshan, Baher Haroun:
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. ISCAS 1994: 351-354 - 1992
- [c3]F. Rouatbi, Baher Haroun, Asim J. Al-Khalili:
Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD 1992: 204-209 - [c2]Baher Haroun, Elie Torbey:
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. ICCD 1992: 174-178
1980 – 1989
- 1989
- [j2]Baher Haroun, Mohamed I. Elmasry:
SPAID: an architectural synthesis tool for DSP custom applications. IEEE J. Solid State Circuits 24(2): 426-435 (1989) - [j1]Baher Haroun, Mohamed I. Elmasry:
Architectural synthesis for DSP silicon compilers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(4): 431-447 (1989) - 1988
- [c1]Baher Haroun, Mohamed I. Elmasry:
Automatic synthesis of a multi-bus architecture for DSP. ICCAD 1988: 44-47
Coauthor Index
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