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2020 – today
- 2024
[c81]Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato:
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks?- a Study of the Effects of "?" for Spoken Dialogue Systems -. LREC/COLING 2024: 4858-4864- [c80]Yui Koyanagi, Tomoaki Ukezono, Toshinori Sato:
A Light-weight and Tamper-resistant AES Implementation by FPGAs. ISCAS 2024: 1-5 - 2023
- [j25]Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Tomoya Mizumoto, Masaya Ohagi, Toshinori Sato:
Building a hospitable and reliable dialogue system for android robots: a scenario-based approach with large language models. Adv. Robotics 37(21): 1364-1381 (2023) - [c79]Hiroyuki Hama, Toshinori Sato:
Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders. GCCE 2023: 902-906 - [c78]Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato
:
Negative Impact of Approximated Signed Addition on Power Reduction. ISDCS 2023: 1-6 - [c77]Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato:
Leveraging Approximate Computing for IoT Image Transmission. ISOCC 2023: 75-76 - [c76]Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono:
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition. ISOCC 2023: 77-78 - [c75]Toshiki Kawamoto, Yuki Okano, Takato Yamazaki, Toshinori Sato, Kotaro Funakoshi, Manabu Okumura:
A Follow-up Study on Evaluation Metrics Using Follow-up Utterances. PACLIC 2023: 552-558 - [c74]Shun Kiyono, Sho Takase, Shengzhe Li, Toshinori Sato:
Bridging the Gap between Subword and Character Segmentation in Pretrained Language Models. RANLP 2023: 568-577 - [c73]Takato Yamazaki, Tomoya Mizumoto, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato:
An Open-Domain Avatar Chatbot by Exploiting a Large Language Model. SIGDIAL 2023: 428-432 - [i4]Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato:
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks? - Investigation of the Effects of Question Marks on Dialogue Systems. CoRR abs/2308.03293 (2023) - [i3]Tatsuya Ide, Eiki Murata, Daisuke Kawahara, Takato Yamazaki, Shengzhe Li, Kenta Shinzato, Toshinori Sato:
PHALM: Building a Knowledge Graph from Scratch by Prompting Humans and a Language Model. CoRR abs/2310.07170 (2023) - 2022
- [c72]Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
An Accuracy-Controllable Approximate Adder for FPGAs. ATAIT 2022: 60-66 - [c71]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge. ACM Great Lakes Symposium on VLSI 2022: 229-235 - [c70]Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato:
Building a Personalized Dialogue System with Prompt-Tuning. NAACL-HLT (Student Research Workshop) 2022: 96-105 - [i2]Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato:
Building a Personalized Dialogue System with Prompt-Tuning. CoRR abs/2206.05399 (2022) - [i1]Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Masaya Ohagi, Tomoya Mizumoto, Shuta Ichimura, Yusuke Kida, Toshinori Sato:
Tourist Guidance Robot Based on HyperCLOVA. CoRR abs/2210.10400 (2022) - 2020
- [j24]Tongxin Yang, Toshinori Sato, Tomoaki Ukezono:
An Accuracy-Configurable Adder for Low-Power Applications. IEICE Trans. Electron. 103-C(3): 68-76 (2020) - [j23]Toshinori Sato, Tomoaki Ukezono:
Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1028-1036 (2020) - [c69]Toshinori Sato, Tomoaki Ukezono:
A Dynamically Configurable Approximate Array Multiplier with Exact Mode. ICCCS 2020: 917-921
2010 – 2019
- 2019
- [j22]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Design and Analysis of Approximate Multipliers with a Tree Compressor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(3): 532-543 (2019) - [j21]Toshinori Sato, Tongxin Yang, Tomoaki Ukezono:
Trading Accuracy for Power with a Configurable Approximate Adder. IEICE Trans. Electron. 102-C(4): 260-268 (2019) - [c68]Toshinori Sato, Tomoaki Ukezono:
Correcting Sign Calculation Errors in Configurable Approximations. APCCAS 2019: 190-193 - [c67]Toshinori Sato, Tomoaki Ukezono:
Tolerating Aging-Induced Timing Violations Via Configurable Approximations. GCCE 2019: 1023-1026 - [c66]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method. ACM Great Lakes Symposium on VLSI 2019: 39-44 - [c65]Tongxin Yang, Toshinori Sato, Tomoaki Ukezono:
A Low-Power Approximate Multiply-Add Unit. ISDCS 2019: 1-4 - [c64]Tongxin Yang, Toshinori Sato, Tomoaki Ukezono:
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. ISVLSI 2019: 385-390 - [c63]Toshinori Sato, Tomoaki Ukezono:
On Applications of Configurable Approximation to Irregular Voltage. NORCAS 2019: 1-6 - [c62]Toshinori Sato, Tomoaki Ukezono:
Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance. PRDC 2019: 23-24 - 2018
- [j20]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2244-2253 (2018) - [c61]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
A low-power high-speed accuracy-controllable approximate multiplier design. ASP-DAC 2018: 605-610 - [c60]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing. ISCAS 2018: 1-5 - [c59]Ryuta Ishida, Toshinori Sato, Tomoaki Ukezono:
Approximate Adder Generation for Image Processing Using Convolutional Neural Network. ISOCC 2018: 38-39 - [c58]Toshinori Sato, Tomoaki Ukezono:
Exploiting Configurability for Correct Sign Calculation in an Approximate Adder. ISOCC 2018: 86-87 - [c57]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
A low-power configurable adder for approximate applications. ISQED 2018: 347-352 - [c56]Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato:
A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing. ISVLSI 2018: 569-574 - 2017
- [c55]Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor. ICCD 2017: 89-96 - 2013
- [c54]Ken Yano, Takanori Hayashida, Toshinori Sato:
Improving timing error tolerance without impact on chip area and power consumption. ISQED 2013: 373-378 - 2012
- [j19]Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida:
A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. 21(6) (2012) - [c53]Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida:
Importance of Single-Core Performance in the Multicore Era. ACSC 2012: 107-114 - [c52]Alex Veidenbaum, Nectarios Koziris, Toshinori Sato, Avi Mendelson:
Topic 4: High-Performance Architecture and Compilers. Euro-Par 2012: 204-205 - [c51]Toshinori Sato, Takanori Hayashida, Ken Yano:
Dynamically reducing overestimated design margin of MultiCores. HPCS 2012: 403-409 - [c50]Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida:
Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT 2012: 822-827 - [c49]Ken Yano, Takanori Hayashida, Toshinori Sato:
Analysis of SER Improvement by Radiation Hardened Latches. PRDC 2012: 89-95 - 2011
- [j18]Yuji Kunitake, Toshinori Sato, Hiroto Yasuura:
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Trans. Electron. 94-C(4): 520-529 (2011) - [c48]Toshinori Sato, Takahito Yoshiki, Takanori Hayashida:
Multicore Power Management Utilizing Error-Predicting Flip-flop. CISIS 2011: 606-611 - 2010
- [c47]Yuji Kunitake, Toshinori Sato, Hiroto Yasuura:
Signal probability control for relieving NBTI in SRAM cells. ISQED 2010: 660-666 - [c46]Yuji Kunitake, Toshinori Sato, Hiroto Yasuura:
A Replacement Strategy for Canary Flip-Flops. PRDC 2010: 227-228
2000 – 2009
- 2009
- [j17]Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura:
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Trans. Electron. 92-C(4): 483-491 (2009) - [c45]Shingo Watanabe, Masanori Hashimoto, Toshinori Sato:
A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407 - [c44]Toshinori Sato, Shingo Watanabe:
Uncriticality-directed scheduling for tackling variation and power challenges. ISQED 2009: 820-825 - 2008
- [j16]Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato:
A Low-Power Instruction Issue Queue for Microprocessors. IEICE Trans. Electron. 91-C(4): 400-409 (2008) - [j15]Toshinori Sato:
A Simple Mechanism for Collapsing Instructions under Timing Speculation. IEICE Trans. Electron. 91-C(9): 1394-1401 (2008) - [c43]Toshinori Sato, Toshimasa Funaki:
Dependability, power, and performance trade-off on a multicore processor. ASP-DAC 2008: 714-719 - [c42]Toshimasa Funaki, Toshinori Sato:
Formulating MITF for a Multicore Processor with SEU Tolerance. DSD 2008: 234-241 - [c41]Toshinori Sato, Shingo Watanabe:
Instruction Scheduling for Variation-Originated Variable Latencies. ISQED 2008: 361-364 - [c40]Shingo Watanabe, Toshinori Sato:
Uncriticality-Directed Low-Power Instruction Scheduling. ISVLSI 2008: 69-74 - [c39]Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato:
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88 - [e1]Jesús Labarta, Kazuki Joe, Toshinori Sato:
High-Performance Computing - 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Lecture Notes in Computer Science 4759, Springer 2008, ISBN 978-3-540-77703-8 [contents] - 2007
- [j14]Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu:
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism. Int. J. Comput. Their Appl. 14(2): 79-91 (2007) - [j13]Kenji Kise, Toshinori Sato, Hironori Nakajo:
Introduction. SIGARCH Comput. Archit. News 35(5): 1-2 (2007) - [c38]Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato:
Indirect Tag Search Mechanism for Instruction Window Energy Reduction. CIT 2007: 841-846 - [c37]Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato:
Challenges in Evaluations for a Typical-Case Design Methodology. ISQED 2007: 374-379 - [c36]Toshinori Sato, Yuji Kunitake:
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. ISQED 2007: 539-544 - [c35]Toshinori Sato, Yuji Kunitake:
Exploiting Input Variations for Energy Reduction. PATMOS 2007: 384-393 - [c34]Toshinori Sato, Toshimasa Funaki:
Power-Performance Trade-Off of a Dependable Multicore Processor. PRDC 2007: 268-273 - 2006
- [j12]Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato:
A leakage-energy-reduction technique for cache memories in embedded processors. J. Embed. Comput. 2(1): 49-55 (2006) - [j11]Akihiro Chiyonobu, Toshinori Sato:
Energy-efficient instruction scheduling utilizing cache miss information. SIGARCH Comput. Archit. News 34(1): 65-70 (2006) - [c33]Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu:
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. PATMOS 2006: 553-562 - [c32]Toshinori Sato, Akihiro Chiyonobu:
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. PRDC 2006: 369-370 - 2005
- [j10]Toshinori Sato, Akihiro Chiyonobu:
An Energy-Efficient Clustered Superscalar Processor. IEICE Trans. Electron. 88-C(4): 544-551 (2005) - [c31]Toshinori Sato:
Exploiting Trivial Computation in Dependable Processors. CATA 2005: 168-173 - [c30]Yuichiro Imaizumi, Toshinori Sato:
Folding Active List for High Performance and Low Power. ISHPC 2005: 33-42 - [c29]Takamasa Tokunaga, Toshinori Sato:
Profiling with Helper Threads. Parallel and Distributed Computing and Networks 2005: 1-6 - 2004
- [j9]Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato:
A leakage-energy-reduction technique for highly-associative caches in embedded systems. SIGARCH Comput. Archit. News 32(3): 50-54 (2004) - [c28]Hidenori Sato, Toshinori Sato:
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. ASP-DAC 2004: 830-833 - [c27]Seiichiro Fujii, Toshinori Sato:
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. EUC 2004: 217-226 - [c26]Masaharu Goto, Toshinori Sato:
Leakage Energy Reduction in Register Renaming. ICDCS Workshops 2004: 890-895 - [c25]Akihiro Chiyonobu, Toshinori Sato:
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. ISICT 2004: 190-195 - [c24]Yuu Tanaka, Toshinori Sato, Takenori Koushiro:
The potential in energy efficiency of a speculative chip-multiprocessor. SPAA 2004: 273-274 - 2003
- [j8]Toshinori Sato, Itsujiro Arita:
Combining variable latency pipeline with instruction reuse for execution latency reduction. Syst. Comput. Jpn. 34(12): 11-21 (2003) - [j7]Takenori Koushiro, Toshinori Sato, Itsujiro Arita:
A trace-level value predictor for Contrail processors. SIGARCH Comput. Archit. News 31(3): 42-47 (2003) - [c23]Asami Tanino, Toshinori Sato:
Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation. CAINE 2003: 282-287 - [c22]Toshinori Sato:
Exploiting Instruction Redundancy for Transient Fault Tolerance. DFT 2003: 547-554 - [c21]Toshinori Sato, Daisuke Morishita:
A field-customizable and runtime-adaptable microarchitecture. FPT 2003: 328-331 - [c20]Akihito Sakanaka, Toshinori Sato:
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. PATMOS 2003: 530-539 - 2002
- [j6]Toshinori Sato, Kiichi Sugitani, Akihiko Hamano:
Evaluating Influence of Compiler Optimizations on Data Speculation. J. Inf. Sci. Eng. 18(6): 1027-1036 (2002) - [j5]Toshinori Sato:
Evaluating the impact of reissued instructions on data speculative processor performance. Microprocess. Microsystems 25(9-10): 469-482 (2002) - [c19]Toshinori Sato, Itsujiro Arita:
Simplifying Instruction Issue Logic in Superscalar Processors. DSD 2002: 341-346 - [c18]Toshinori Sato, Itsujiro Arita:
Low-Cost Value Predictors Using Frequent Value Locality. ISHPC 2002: 106-119 - [c17]Toshinori Sato, Itsujiro Arita:
Reducing Energy Consumption via Low-Cost Value Prediction. PATMOS 2002: 380-389 - [c16]Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita:
The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. PDPTA 2002: 1010-1016 - 2001
- [c15]Toshinori Sato, Itsujiro Arita:
Tolerating Transient Faults through an Instruction Reissue Mechanism. PDCS 2001: 240-247 - [c14]Toshinori Sato, Itsujiro Arita:
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. Euro-Par 2001: 428-438 - [c13]Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita:
Influence of Compiler Optimizations on Value Prediction. HPCN Europe 2001: 312-321 - [c12]Toshinori Sato, Itsujiro Arita:
In Search of Efficient Reliable Processor Design. ICPP 2001: 525-532 - [c11]Toshinori Sato, Itsujiro Arita:
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. PRDC 2001: 225-232 - 2000
- [j4]Toshinori Sato:
Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism. J. Syst. Archit. 46(13): 1231-1252 (2000) - [j3]Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki:
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. IEEE J. Solid State Circuits 35(7): 1025-1033 (2000) - [j2]Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki:
Vector Unit Architecture for Emotion Synthesis. IEEE Micro 20(2): 40-47 (2000) - [c10]Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu:
300MHz design methodology of VU for emotion synthesis. ASP-DAC 2000: 635-640 - [c9]Toshinori Sato, Itsujiro Arita:
Partial Resolution in Data Value Predictors. ICPP 2000: 69-76 - [c8]Toshinori Sato, Itsujiro Arita:
Table size reduction for data value predictors by exploiting narrow width values. ICS 2000: 196-205 - [c7]Toshinori Sato, Itsujiro Arita:
Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN 2000: 78-87 - [c6]Toshinori Sato, Itsujiro Arita:
The KIT COSMOS Processor: Introducing CONDOR. PDPTA 2000
1990 – 1999
- 1999
- [j1]Toshinori Sato:
A Simulation Study of Combining Load Value and Address Predictors. Int. J. High Speed Comput. 10(3): 301-325 (1999) - [c5]Toshinori Sato:
A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. EUROMICRO 1999: 1178-1185 - [c4]Toshinori Sato:
Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. Euro-Par 1999: 1281-1290 - [c3]Toshinori Sato:
Profile-Based Selection of Load Value and Address Predictors. ISHPC 1999: 17-28 - 1998
- [c2]Toshinori Sato:
Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. EUROMICRO 1998: 10285-10292 - 1997
- [c1]Toshinori Sato:
Data Dependence Path Reductio with Tunneling Load Instructions. ISHPC 1997: 119-130
Coauthor Index
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