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ORCIDSiva G. Narendra
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2010 – 2019
- 2012
[c28]Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra:
Performance analysis of CNFET based circuits in the presence of fabrication imperfections. ISCAS 2012: 1363-1366- 2010
- [c27]Siva Narendra:
Benefits and barriers for probabilistic design. ASP-DAC 2010: 626-627 - [c26]Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Yield enhancement by tube redundancy in CNFET-based circuits. ICECS 2010: 442-445 - [c25]Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva Narendra:
The semiconductor industry in 2025. ISSCC 2010: 534-535 - [c24]Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. NANOARCH 2010: 71-76
2000 – 2009
- 2008
- [j7]David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(1): 3-5 (2008) - [c23]Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Carbon nanotube circuit design choices in the presence of metallic tubes. ISCAS 2008: 177-180 - [c22]Eugenio Cantatore, Siva Narendra:
Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum). ISSCC 2008: 656-657 - 2007
- [c21]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - [c20]Donhee Ham, Siva Narendra:
TD: Trends in Wireless Systems. ISSCC 2007: 566-567 - 2005
- [j6]Siva Narendra:
Challenges and design choices in nanoscale CMOS. ACM J. Emerg. Technol. Comput. Syst. 1(1): 7-49 (2005) - [j5]Volkan Kursun
, Vivek De, Eby G. Friedman, Siva G. Narendra:
Monolithic voltage conversion in low-voltage CMOS technologies. Microelectron. J. 36(9): 863-867 (2005) - [c19]James W. Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. ISCAS (1) 2005: 9-12 - [c18]Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra:
Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467 - 2004
- [j4]Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman:
Low-voltage-swing monolithic dc-dc conversion. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 241-248 (2004) - [c17]Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De:
Design optimizations for microprocessors at low temperature. DAC 2004: 2-5 - [c16]Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De:
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED 2004: 263-268 - [c15]Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman:
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521 - [c14]Siva Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar:
Design Challenges in Sub-100nm High Performance Microprocessors. VLSI Design 2004: 15-17 - [c13]K. Narasimhulu, Siva Narendra, V. Ramgopal Rao:
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. VLSI Design 2004: 545-550 - 2003
- [j3]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 514-522 (2003) - [c12]Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC 2003: 617-620 - [c11]Shekhar Borkar, Tanay Karnik, Siva Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 - [c10]Stephen Tang, Siva Narendra, Vivek De:
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. ISLPED 2003: 199-204 - [c9]Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279- - 2002
- [b1]Siva G. Narendra:
Effect of Metal oxide semiconductor field-effect transistors threshold voltage variation on high-performance circuits. Massachusetts Institute of Technology, Cambridge, MA, USA, 2002 - [j2]Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. 19(5): 36-43 (2002) - [j1]Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 91-95 (2002) - [c8]James Kao, Siva Narendra, Anantha P. Chandrakasan:
Subthreshold leakage modeling and reduction techniques. ICCAD 2002: 141-148 - [c7]Siva Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED 2002: 19-23 - [c6]Ron Wilson, Siva Narendra, Vivek De:
Evening Panel Discussion: Process Variation: Is It Too Much to Handle? ISQED 2002: 213- - 2001
- [c5]James W. Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 - [c4]Siva Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar:
Scaling of stack effect and its application for leakage reduction. ISLPED 2001: 195-200 - [c3]Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De:
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED 2001: 207-212
1990 – 1999
- 1999
- [c2]Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 - 1998
- [c1]James Kao, Siva Narendra, Anantha P. Chandrakasan:
MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. DAC 1998: 495-500
Coauthor Index
aka: Vivek K. De
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