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2020 – today
- 2024
[c20]Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung:
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. VLSID 2024: 443-448- 2023
- [j2]Mohammad Rahmani Fadiheh
, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. IEEE Trans. Computers 72(1): 222-235 (2023) - [c19]Anupam Golder, Debayan Das, Santosh Ghosh, Avinash Varna, Majid Sabbagh, Sayak Ray, Rana Elnaggar, Joseph Friel, Daniel Dinu, Jason M. Fung:
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. DAC 2023: 1-6 - [c18]Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz:
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. ICCAD 2023: 1-9 - 2022
- [c17]Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton:
Automating hardware security property generation: invited. DAC 2022: 1384-1387 - 2021
- [i2]Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. CoRR abs/2108.01979 (2021)
2010 – 2019
- 2019
- [c16]Sayak Ray, Nishant Ghosh, Ramya Jayaram Masti, Arun K. Kanuparthi, Jason M. Fung:
Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs. DAC 2019: 43 - [c15]Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray:
Verification of Authenticated Firmware Loaders. FMCAD 2019: 110-119 - [i1]Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray:
Verification of Authenticated Firmware Load. IACR Cryptol. ePrint Arch. 2019: 564 (2019) - 2018
- [c14]Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik:
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. DAC 2018: 91:1-91:6 - 2017
- [c13]Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik:
Malware detection using machine learning based analysis of virtual memory access patterns. DATE 2017: 169-174 - 2015
- [c12]Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury:
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies. ASP-DAC 2015: 366-371 - [c11]Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik:
Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. FMCAD 2015: 160-167 - [c10]Pramod Subramanyan, Sayak Ray, Sharad Malik:
Evaluating the security of logic encryption algorithms. HOST 2015: 137-143 - 2014
- [c9]Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC 2014: 250-255 - [c8]Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB 2014: 623-624 - [c7]Sayak Ray, Sharad Malik:
Effective abstraction for response proof of communication fabrics. NOCS 2014: 188-189 - 2013
- [b1]Sayak Ray:
Scalable Model Checking Beyond Safety - A Communication Fabric Perspective. University of California, Berkeley, USA, 2013 - [c6]Sayak Ray, Robert K. Brayton:
Ranking structure in communication fabrics. MEMOCODE 2013: 65-74 - 2012
- [j1]Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan:
A dynamic assertion-based verification platform for validation of UML designs. ACM SIGSOFT Softw. Eng. Notes 37(1): 1-14 (2012) - [c5]Sayak Ray, Robert K. Brayton:
Scalable progress verification in credit-based flow-control systems. DATE 2012: 905-910 - [c4]Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. DATE 2012: 1579-1584 - 2011
- [c3]Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton:
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD 2011
2000 – 2009
- 2008
- [c2]Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan:
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. ATVA 2008: 222-227 - 2007
- [c1]Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti:
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. VLSI Design 2007: 95-102
Coauthor Index
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