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ORCIDTakashi Imagawa
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2020 – today
- 2023
[j7]Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi:
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. IPSJ Trans. Syst. LSI Des. Methodol. 16: 35-44 (2023)- [c18]Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi:
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. ASICON 2023: 1-4 - [c17]Renya Makimoto, Takashi Imagawa, Hiroyuki Ochi:
Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. SOCC 2023: 1-6 - 2021
- [c16]Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto
, Hiroyuki Ochi:
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE 2021: 838-843 - 2020
- [c15]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2018
- [j6]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [c14]Yoshikazu Miyanaga, Junji Yamano, Masaki Miura, Tohru Gotoh, Takashi Imagawa, Hiroshi Tsutsui:
Development of Real-time FHD Loss-Less Video Communication over an $8\times 8$ MIMO-OFDM System. APSIPA 2018: 1087-1090 - [c13]Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano, Takashi Imagawa, Hiroshi Tsutsui:
Development of High Performance RF Modules Used in Real-time FHD Video Communication over 8x8 MIMO-OFDM System. ISPACS 2018: 107-110 - 2017
- [c12]Yoshikazu Miyanaga, Hiroshi Tsutsui, Takashi Imagawa:
FHD loss-less video communication over 8 × 8 MIMO-OFDM. ISCIT 2017: 1-5 - [c11]Takashi Imagawa, Koki Honda, Hiroyuki Ochi:
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. SoCC 2017: 80-85 - [c10]Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi:
Selectable grained reconfigurable architecture (SGRA) and its design automation. SoCC 2017: 196-201 - 2016
- [c9]Dabwitso Kasauka, Hiroshi Tsutsui, Seijiro Imai, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga:
Image smoothing in the spatial domain using multigrid conjugate gradient methods based on accelerated iterative shrinkage. APSIPA 2016: 1-5 - [c8]Seijiro Imai, Dabwitso Kasauka, Hiroshi Tsutsui, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga:
Processing time reduction of tone mapping based on iterative shrinkage smoothing using parallel processing. ISPACS 2016: 1-4 - 2015
- [j5]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. 98-C(7): 741-750 (2015) - [c7]Dabwitso Kasauka, Hiroshi Tsutsui, Hiroyuki Okuhata, Takashi Imagawa, Yoshikazu Miyanaga:
Image smoothing using spatial iterative methods based on accelerated iterative shrinkage. APSIPA 2015: 779-783 - [c6]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - 2014
- [j4]Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1468-1482 (2014) - [j3]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - 2013
- [j2]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. 96-C(4): 454-462 (2013) - [c5]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE 2013: 701-706 - [c4]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED 2013: 538-545 - [c3]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye:
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig 2013: 1-6 - 2010
- [j1]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2524-2532 (2010) - [c2]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC 2010: 248-253
2000 – 2009
- 2009
- [c1]Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye:
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192
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