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ORCIDCong Xu 0002
Person information
- affiliation: University of California Santa Barbara (UCSB), CA, USA
- affiliation: Hewlett Packard Labs, Palo Alto, CA, USA
- affiliation (PhD 2015): Pennsylvania State University, PA, USA
Other persons with the same name
- Cong Xu — disambiguation page
- Cong Xu 0001
![[0000-0002-9288-1743]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-9288-1743")
— Inspur (Beijing) Electronic Information Industry Company, Ltd., Beijing, China (and 1 more) - Cong Xu 0003 — Changsha University of Science and Technology, School of Computer and Communication Engineering, China (and 1 more)
- Cong Xu 0004 — Harbin Institute of Technology (HIT), Faculty of Computing, Heilongjiang, China
- Cong Xu 0005 — East China Normal University (ECNU), School of Computer Science and Technology, Shanghai, China (and 1 more)
- Cong Xu 0006 — University of California - Davis (UCD), Department of Statistics, CA, USA
- Cong Xu 0007 — University of Canterbury, School of Forestry, Christchurch, New Zealand
- Cong Xu 0008 — Auburn University, Department of Computer Science and Software Engineering, AL, USA
- Cong Xu 0009 — Central South University, School of Computer Science and Engineering, Changsha, China
- Cong Xu 0010 — IIT Bombay, India (and 1 more)
- Cong Xu 0011 — Capital Normal University, School of Mathematical Sciences, Beijing, China (and 1 more)
- Cong Xu 0012 — Harbin Normal University, China
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2020 – today
- 2022
[j8]Xinying Wang, Cong Xu, Ke Wang, Feng Yan, Dongfang Zhao:
Memory Scaling of Cloud-Based Big Data Systems: A Hybrid Approach. IEEE Trans. Big Data 8(5): 1259-1272 (2022)
2010 – 2019
- 2019
- [j7]Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei:
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. 30(1): 146-160 (2019) - 2018
- [c33]Xinying Wang, Cong Xu, Ke Wang, Feng Yan, Dongfang Zhao:
Toward Cost-Effective Memory Scaling in Clouds: Symbiosis of Virtual and Physical Memory. IEEE CLOUD 2018: 33-40 - [i3]Wei Wen, Yandan Wang, Feng Yan, Cong Xu, Yiran Chen, Hai Li:
SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning. CoRR abs/1805.07898 (2018) - 2017
- [c32]Wei Wen, Cong Xu, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
Coordinating Filters for Faster Deep Neural Networks. ICCV 2017: 658-666 - [c31]Wei Wen, Cong Xu, Feng Yan, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning. NIPS 2017: 1509-1519 - [i2]Wei Wen, Cong Xu, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
Coordinating Filters for Faster Deep Neural Networks. CoRR abs/1703.09746 (2017) - [i1]Wei Wen, Cong Xu, Feng Yan, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning. CoRR abs/1705.07878 (2017) - 2016
- [j6]Jishen Zhao, Cong Xu, Tao Zhang, Yuan Xie:
BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories. J. Comput. Sci. Technol. 31(1): 20-35 (2016) - [c30]Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen:
NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation. DAC 2016: 70:1-70:6 - [c29]Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie:
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. DAC 2016: 173:1-173:6 - [c28]Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie:
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. ICCAD 2016: 2 - [c27]Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie:
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. ISCA 2016: 27-39 - 2015
- [j5]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. Inf. Media Technol. 10(2): 182-191 (2015) - [j4]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. IPSJ Trans. Syst. LSI Des. Methodol. 8: 2-11 (2015) - [j3]Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie:
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. 1(4): 195-206 (2015) - [j2]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. 20(4): 63:1-63:21 (2015) - [c26]Yang Zheng, Cong Xu, Yuan Xie:
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues. ASP-DAC 2015: 112-117 - [c25]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie:
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - [c24]Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi:
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - 2014
- [c23]Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie:
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC 2014: 825-830 - [c22]Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie:
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. ACM Great Lakes Symposium on VLSI 2014: 51-56 - [c21]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI 2014: 145-150 - [c20]Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie:
TSV power supply array electromigration lifetime analysis in 3D ICS. ACM Great Lakes Symposium on VLSI 2014: 239-240 - [c19]Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie:
Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA 2014: 13-24 - [c18]Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie:
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. HPCA 2014: 368-379 - [c17]Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD 2014: 55-62 - [c16]Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie:
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. ICCAD 2014: 301-308 - [c15]Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie:
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. ISCA 2014: 349-360 - [c14]Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie:
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. ISQED 2014: 639-644 - 2013
- [c13]Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC 2013: 108:1-108:6 - [c12]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD 2013: 17-23 - [c11]Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie:
Low power multi-level-cell resistive memory design with incomplete data mapping. ICCD 2013: 131-137 - [c10]Tao Zhang, Cong Xu, Yuan Xie, Guangyu Sun:
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. ICCD 2013: 138-144 - 2012
- [j1]Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi:
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 994-1007 (2012) - [c9]Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan:
When to forget: A system-level perspective on STT-RAMs. ASP-DAC 2012: 311-316 - [c8]Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das:
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC 2012: 243-252 - [c7]Guangyu Sun, Cong Xu, Yuan Xie:
Modeling and design exploration of FBDRAM as on-chip memory. DATE 2012: 1507-1512 - [c6]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214 - 2011
- [c5]Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
Design implications of memristor-based RRAM cross-point structures. DATE 2011: 734-739 - [c4]Jishen Zhao, Cong Xu, Yuan Xie:
Bandwidth-aware reconfigurable cache design with hybrid memory technologies. ICCAD 2011: 48-55 - [c3]Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie:
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD 2011: 463-470 - [c2]Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen:
Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA 2011: 377-388 - 2010
- [c1]Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie:
Impact of process variations on emerging memristor. DAC 2010: 877-882
Coauthor Index
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