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ORCIDICCAD 2013: San Jose, California, USA
- Jörg Henkel:
The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013. IEEE 2013, ISBN 978-1-4799-1069-4
Emerging memory technologies
- Wujie Wen
, Mengjie Mao, Xiaochun Zhu, Seung-Hyuk Kang, Danghui Wang, Yiran Chen:
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. 1-8 - Yaojun Zhang, Ismail Bayram, Yu Wang, Hai Li, Yiran Chen:
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. 9-16 - Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. 17-23
Novel techniques for manufacturability and layout migration
- Pei-Ci Wu, Tan Yan, Hongbo Zhang, Martin D. F. Wong:
Efficient aerial image simulation on multi-core SIMD CPU. 24-31 - Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong:
Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time. 32-39 - Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin:
Efficient analog layout prototyping by layout reuse with routing preservation. 40-47
Making timing variations irrelevant
- Rong Ye, Ting Wang, Feng Yuan, Rakesh Kumar, Qiang Xu:
On reconfiguration-oriented approximate adder design and its application. 48-54 - Jie Zhang, Feng Yuan, Rong Ye, Qiang Xu:
ForTER: a forward error correction scheme for timing error resilience. 55-60 - Mojtaba Ebrahimi, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori:
Aging-aware logic synthesis. 61-68
Advances in modeling and optimization: from system level to mixed signal designs
- Girish Venkataramani, Kiran Kintali, Sudeepa Prakash, Stephan van Beek:
Model-based hardware design. 69-73 - John Crossley, Alberto Puggelli, Hanh-Phuc Le, B. Yang, R. Nancollas, Kwangmo Jung, Lingkai Kong, Nathan Narevsky, Yue Lu, Nicholas Sutardja, E. J. An, Alberto L. Sangiovanni-Vincentelli, Elad Alon:
BAG: a designer-oriented integrated framework for the development of AMS circuit generators. 74-81
Performance evaluation of multicore systems: from traffic analysis to latency predictions
- Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). 82-84
Improving test quality, manufacturability & reliability
- Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Improved SAT-based ATPG: more constraints, better compaction. 85-90 - Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li:
Automatic test pattern generation for delay defects using timed characteristic functions. 91-98 - Ronald D. Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li:
DREAMS: DFM rule EvAluation using manufactured silicon. 99-106 - Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye:
Stochastic error rate estimation for adaptive speed control with field delay testing. 107-114
CAD approaches for emerging applications
- Chung-Wei Lin, Qi Zhu, Calvin Phung, Alberto L. Sangiovanni-Vincentelli:
Security-aware mapping for CAN-based real-time distributed automotive systems. 115-121 - Hao Chen, Can Hankendi, Michael C. Caramanis, Ayse K. Coskun:
Dynamic server power capping for enabling data center participation in power markets. 122-129 - Yongtae Kim, Yong Zhang, Peng Li:
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems. 130-137 - Anja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi:
PROTON: an automatic place-and-route tool for optical networks-on-chip. 138-145
From application to emerging devices: analog is between a rock and a hard place
- Trent McConaghy:
Analog behavior in custom IC variation-aware design. 146-148 - David White:
A new methodology to address the growing productivity gap in analog design. 149-152
Keeping kilo-core chips cool: new directions and emerging solutions
- Muhammad Shafique, Jörg Henkel:
Agent-based distributed power management for kilo-core processors. 153-160 - Ümit Y. Ogras, Raid Zuhair Ayoub, Michael Kishinevsky, David Kadjo:
Managing mobile platform power. 161-162
Triple patterning, triple the trouble?
- Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan:
A high-performance triple patterning layout decomposer with balanced density. 163-169 - Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. 170-177 - Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
Constrained pattern assignment for standard cell based triple patterning lithography. 178-185 - Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma:
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. 186-193
Emerging design automation: the movement to apply CAD techniques to global challenges
- Younghyun Kim, Donghwa Shin, Massimo Petricca, Sangyoung Park, Massimo Poncino, Naehyuck Chang:
Computer-aided design of electrical energy systems. 194-201 - Qiuwen Chen, Qinru Qiu, Hai Li, Qing Wu:
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring. 202-205 - Alex K. Jones, Yiran Chen, William O. Collinge, Haifeng Xu, Laura A. Schaefer, Amy E. Landis, Melissa M. Bilec:
Considering fabrication in sustainable computing. 206-210
Emerging directions in hardware synthesis
- Zhiru Zhang, Bin Liu:
SDC-based modulo scheduling for pipeline synthesis. 211-218 - Mehrdad Najibi, Peter A. Beerel:
Slack matching mode-based asynchronous circuits for average-case performance. 219-225 - Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Sensitization criterion for threshold logic circuits and its application. 226-233 - Jason Thong, Nicola Nicolici:
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. 234-241
Thermal management
- Qing Xie, Jaemin Kim, Yanzhi Wang, Donghwa Shin, Naehyuck Chang, Massoud Pedram:
Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor. 242-247 - Muhammad Ismail, Osman Hasan, Thomas Ebi, Muhammad Shafique, Jörg Henkel:
Formal verification of distributed dynamic thermal management. 248-255 - Arvind Sridhar, Yassir Madhour, David Atienza, Thomas Brunschwiler, John Richard Thome:
STEAM: a fast compact thermal model for two-phase cooling of integrated circuits. 256-263
2013 CAD contest
- Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan:
The overview of 2013 CAD contest at ICCAD. 264 - Chih-Jen Hsu, Wei-Hsun Lin, Hwei-Tseng Wang, Feng Lu, Kei-Yong Khoo:
ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite. 265-267 - Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert:
ICCAD-2013 CAD contest in placement finishing and benchmark suite. 268-270 - Shayak Banerjee, Zhuo Li, Sani R. Nassif:
ICCAD-2013 CAD contest in mask optimization and benchmark suite. 271-274
Modelling of through silicon vias parasitics and shallow trench isolation stress effects
- Zao Liu, Sahana Swarup, Sheldon X.-D. Tan:
Compact lateral thermal resistance modeling and characterization for TSV and TSV array. 275-280 - Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. 281-288 - Sravan K. Marella, Sachin S. Sapatnekar:
The impact of shallow trench isolation effects on circuit performance. 289-294
System-level and post-silicon validation
- Lingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan:
Diagnosing root causes of system level performance violations. 295-302 - Kai Cong, Fei Xie, Li Lei:
Automatic concolic test generation with virtual prototypes for post-silicon validation. 303-310 - Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco:
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. 311-317
Power considerations in system design
- Hao Wang, Abhishek A. Sinkar, Nam Sung Kim:
Improving platform energy: chip area trade-off in near-threshold computing environment. 318-325 - Abhinav Agarwal, Arvind:
Leveraging rule-based designs for automatic power domain partitioning. 326-333 - Youngtaek Kim, Lizy Kurian John, Indrani Paul, Srilatha Manne, Michael J. Schulte:
Performance boosting under reliability and power constraints. 334-341
Placement
- Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. 342-348 - Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan:
Methodology for standard cell compliance and detailed placement for triple patterning lithography. 349-356 - Tao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev:
POLAR: placement based on novel rough legalization and refinement. 357-362
Lifetime analysis of TSV-based 3D ICs
- Xin Zhao, Yang Wan, Michael Scheuermann, Sung Kyu Lim:
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs. 363-370 - Chun Zhang, Moongon Jung, Sung Kyu Lim, Yiyu Shi:
Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives. 371-378 - Jiwoo Pak, Sung Kyu Lim, David Z. Pan:
Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. 379-386
Test and security for analog and mixed-signal circuits
- Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti:
Scalable and efficient analog parametric fault identification. 387-392 - S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang:
An IDDQ-based source driver IC design-for-test technique. 393-398 - Yu Liu, Yier Jin, Yiorgos Makris:
Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation. 399-404
To remember or not: embedded memories
- Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel:
AMBER: adaptive energy management for on-chip hybrid video memories. 405-412 - Po-Yang Hsu, TingTing Hwang:
Thread-criticality aware dynamic cache reconfiguration in multi-core system. 413-420 - Yu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Hsiang-Pang Li, Yung-Chun Li:
A disturb-alleviation scheme for 3D flash memory. 421-428 - Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li:
Unleashing the potential of MLC STT-RAM caches. 429-436
Power, timing and noise analysis and optimization
- Tao Wang, Chun Zhang, Jinjun Xiong, Yiyu Shi:
Eagle-eye: a near-optimal statistical framework for noise sensor placement. 437-443 - Xue Lin, Yanzhi Wang, Massoud Pedram:
Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method. 444-449 - Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar:
High-performance gate sizing with a signoff timer. 450-457 - Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez:
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. 458-465
Intelligent compilation for emulation and acceleration
- Michael D. Moffitt, Gernot E. Günther, Kevin A. Pasnik:
Place and route for massively parallel hardware-accelerated functional verification. 466-472 - Platon Beletsky, Michael Bershteyn, Alexandre Birguer, Chunkuen Ho, Viktor Salitrennik:
Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems. 473-477
Analog and RF
- Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu:
Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space. 478-485 - Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim:
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. 486-493 - Lengfei Han, Xueqian Zhao, Zhuo Feng:
An efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuits. 494-499 - Ahmet Gokcen Mahmutoglu, Alper Demir, Jaijeet S. Roychowdhury:
Modeling and analysis of (nonstationary) low frequency noise in nano devices: a synergistic approach based on stochastic chemical kinetics. 500-507
Efficient and secure embedded processors
- Janmartin Jahn, Santiago Pagani, Jian-Jia Chen, Jörg Henkel:
MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers. 508-515 - Xiaolong Xie, Yun Liang, Guangyu Sun, Deming Chen:
An efficient compiler framework for cache bypassing on GPUs. 516-523 - Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk:
A just-in-time customizable processor. 524-531 - Domenic Forte, Chongxi Bao, Ankur Srivastava:
Temperature tracking: an innovative run-time approach for hardware Trojan detection. 532-539
Novel EM-IR for power grids
- Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm:
Redundancy-aware electromigration checking for mesh power grids. 540-547 - Jia Wang, Xuanxing Xiong:
Scalable power grid transient analysis via MOR-assisted time-domain simulations. 548-552 - Mohammad Fawaz, Sandeep Chatterjee, Farid N. Najm:
A vectorless framework for power grid electromigration checking. 553-560 - Xuexin Liu, Hai Wang, Sheldon X.-D. Tan:
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms. 561-568
FinFET: a multifaceted perspective for CAD engineers
- Rasit Onur Topaloglu:
Design with FinFETs: design rules, patterns, and variability. 569-571
Beyond charge-based computing
- Arijit Raychowdhury:
Spin torque devices in embedded memory: model studies and design space exploration. 572-575 - Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Exploring Boolean and non-Boolean computing with spin torque devices. 576-580
Verification of large scale designs
- Harry Foster:
Why the design productivity gap never happened. 581-584
Tree optimization in physical synthesis
- Hua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri:
Depth controlled symmetric function fanin tree restructure. 585-591 - Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin:
In-placement clock-tree aware multi-bit flip-flop generation for power optimization. 592-598 - Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. 599-606
New frontiers in EDA for neural and microfluidic circuits
- Hugh T. Blair, Jason Cong, Di Wu:
FPGA simulation engine for customized construction of neural microcircuits. 607-614 - Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang:
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing. 615-621 - Yan Luo, Bhargab B. Bhattacharya, Tsung-Yi Ho, Krishnendu Chakrabarty:
Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip. 622-629
Customized and heterogeneous architectures
- Jason Cong, Bingjun Xiao:
Optimization of interconnects between accelerators and shared memories in dark silicon. 630-637 - Karthick Parashar, Daniel Ménard, Olivier Sentieys:
A polynomial time algorithm for solving the word-length optimization problem. 638-645 - Tuo Li, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. 646-653 - Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
Trace alignment algorithms for offline workload analysis of heterogeneous architectures. 654-661
Formal and symbolic verification
- Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi, Xin Chen, Erika Ábrahám:
From statistical model checking to statistical model inference: characterizing the effect of process variations in analog circuits. 662-669 - Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
Hardware implementation of BLTL property checkers for acceleration of statistical model checking. 670-676 - Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer:
Proof logging for computer algebra based SMT solving. 677-684 - Chun-Nan Chou, Chen-Kai Chu, Chung-Yang (Ric) Huang:
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation. 685-690
Clock synthesis, ECO, and PCB routing
- Heechun Park, Taewhan Kim:
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. 691-696 - Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou:
Low-power timing closure methodology for ultra-low voltage designs. 697-704 - Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath:
Incremental multiple-scan chain ordering for ECO flip-flop insertion. 705-712 - Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-route alleviation of dense meander segments in high-performance printed circuit boards. 713-720
Just like how we designed VLSI circuit and system: design automation is also essential to system biology
- Hua Jiang, Marc D. Riedel, Keshab K. Parhi:
Digital logic with molecular reactions. 721-727 - Cheng-Ju Pan, Hsiao-Chun Huang:
Noise in genetic circuits: hindrance or chance? 728-731
Emerging system level design
- Naman Saraf, Kia Bazargan:
Sequential logic to transform probabilities. 732-738 - Nicolas Fournel, Luc Michel, Frédéric Pétrot:
Automated generation of efficient instruction decoders for instruction set simulators. 739-746 - Daniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim:
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. 747-754 - Rana Muhammad Bilal, Rehan Hafiz, Muhammad Shafique, Saad Shoaib, Asim Munawar, Jörg Henkel:
ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures. 755-762
Advances in logic synthesis
- Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Generalized Boolean symmetries through nested partition refinement. 763-770 - Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, Meng-Yen Li:
Encoding multi-valued functions for symmetry. 771-778 - Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Approximate logic synthesis under general error magnitude and frequency constraints. 779-786 - Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto:
Partial synthesis through sampling with and without specification. 787-794
Stochastic circuit simulation
- Xin Li, Fa Wang, Shupeng Sun, Chenjie Gu:
Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits. 795-802 - Zheng Zhang, Ibrahim M. Elfadel, Luca Daniel:
Uncertainty quantification for integrated circuits: stochastic spectral methods. 803-810 - Alper Demir, Burak Erman:
Simulation of temporal stochastic phenomena in electronic and biological systems: a comparative review, examples and synergies. 811-818
Trustworthy hardware
- Masoud Rostami, Farinaz Koushanfar, Jeyavijayan Rajendran, Ramesh Karri:
Hardware security: threat models and metrics. 819-823 - Yier Jin, Yiorgos Makris:
A proof-carrying based framework for trusted microprocessor IP. 824-829 - Garrett S. Rose, Nathan R. McDonald, Lok-Kwong Yan, Bryant T. Wysocki:
A write-time based memristive PUF for hardware security applications. 830-833
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