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ORCIDSabyasachi Deyati
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2020 – today
- 2023
[j4]Sabyasachi Deyati
, Barry John Muldrey, Abhijit Chatterjee:
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems. J. Electron. Test. 39(3): 303-322 (2023)- 2021
- [j3]Sabyasachi Deyati, Barry J. Muldrey, Adit D. Singh, Abhijit Chatterjee:
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. J. Electron. Test. 37(1): 41-63 (2021) - 2020
- [j2]Sabyasachi Deyati, Barry J. Muldrey, Abhijit Chatterjee:
Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2006-2019 (2020)
2010 – 2019
- 2017
- [b1]Sabyasachi Deyati:
Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. Georgia Institute of Technology, Atlanta, GA, USA, 2017 - [c19]Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. DATE 2017: 274-277 - [c18]Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee:
Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. ITC 2017: 1-10 - [c17]Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee:
Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. VLSID 2017: 403-408 - 2016
- [c16]Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee:
Noise-Resilient SRAM Physically Unclonable Function Design for Security. ATS 2016: 55-60 - [c15]Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee:
Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits. ATS 2016: 96-101 - [c14]Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
Trojan detection in digital systems using current sensing of pulse propagation in logic gates. ISQED 2016: 350-355 - [c13]Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee:
DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems. ITC 2016: 1-10 - [c12]Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. VLSID 2016: 463-468 - [c11]Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
Adaptive testing of analog/RF circuits using hardware extracted FSM models. VTS 2016: 1-6 - 2015
- [c10]Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. ATS 2015: 127-132 - 2014
- [j1]Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee:
Low Cost Signal Reconstruction Based Testing of RF Components using Incoherent Undersampling. J. Electron. Test. 30(2): 213-228 (2014) - [c9]Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. ATS 2014: 200-205 - [c8]Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang:
A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. ITC 2014: 1-10 - [c7]Sabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee:
Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. VTS 2014: 1-6 - 2013
- [c6]Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee:
Low cost signal reconstruction based testing of RF components using incoherent undersampling. LATW 2013: 1-5 - [c5]Sabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee:
VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests. VLSI Design 2013: 314-319 - [c4]Barry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee:
RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning. VTS 2013: 1-6 - 2012
- [c3]Abhijit Chatterjee, Sabyasachi Deyati, Barry John Muldrey, Shyam Kumar Devarakond, Aritra Banerjee:
Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits. ICCAD 2012: 553-556 - [c2]Sabyasachi Deyati, Aritra Banerjee, Abhijit Chatterjee:
Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis. IOLTS 2012: 142-145 - 2011
- [c1]Sabyasachi Deyati, Pradip Mandal:
An automated design methodology for yield aware analog circuit synthesis in submicron technology. ISQED 2011: 229-235
Coauthor Index
aka: Barry J. Muldrey
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