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Wen-Hao Liu 0001

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affiliation: NVIDIA, Hsinchu, Taiwan

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Journal Articles

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2022
[j6]
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Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu:
In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 784-788 (2022)
[j5]
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Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang:
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1957-1970 (2022)
2018
[j4]
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Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018)
2015
[j3]
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Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 502-514 (2015)
2013
[j2]
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Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 709-722 (2013)
2012
[j1]
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Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 459-472 (2012)

Conference and Workshop Papers

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2024
[c33]
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Wen-Hao Liu, Anthony Agnesina, Haoxing Mark Ren:
Challenges for Automating PCB Layout. ISPD 2024: 91-92
[c32]
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Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren:
GPU/ML-Enhanced Large Scale Global Routing Contest. ISPD 2024: 269-274
2022
[c31]
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Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin:
Challenges for Automating Package Routing. ISPD 2022: 193-194
[c30]
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Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. VLSI-SoC 2022: 1-6
[c29]
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Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC 2022: 1-6
2021
[c28]
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  - conf/date/ZhuangHLGQL21
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Zhen Zhuang, Xing Huang, Genggeng Liu, Wenzhong Guo, Weikang Qian, Wen-Hao Liu:
ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification. DATE 2021: 1570-1573
2020
[c27]
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Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang:
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE 2020: 586-591
[c26]
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Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo:
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. ACM Great Lakes Symposium on VLSI 2020: 107-112
2019
[c25]
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Necati Uysal, Wen-Hao Liu, Rickard Ewetz:
Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew. ASP-DAC 2019: 761-766
[c24]
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Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser:
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD 2019: 147-151
2018
[c23]
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Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu:
ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD 2018: 140-143
2017
[c22]
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  - conf/aspdac/HanLEKCW17
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Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. ASP-DAC 2017: 456-462
2016
[c21]
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Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang:
Negotiation-based track assignment considering local nets. ASP-DAC 2016: 378-383
[c20]
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Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7
2014
[c19]
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Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang:
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. DAC 2014: 5:1-5:6
[c18]
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Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang:
Density-aware Detailed Placement with Instant Legalization. DAC 2014: 122:1-122:6
[c17]
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Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. DATE 2014: 1-6
[c16]
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Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI 2014: 129-134
[c15]
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Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang:
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. ICCAD 2014: 389-396
[c14]
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Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
A study on unroutable placement recognition. ISPD 2014: 19-26
[c13]
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  - conf/ispd/YutsisBCSL14
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Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu:
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. ISPD 2014: 161-168
[c12]
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Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li:
Skillfully diminishing antenna effect in layer assignment stage. VLSI-DAT 2014: 1-4
2013
[c11]
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Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8
[c10]
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Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Optimization of placement solutions for routability. DAC 2013: 153:1-153:9
[c9]
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Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD 2013: 114-119
2012
[c8]
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  - conf/aspdac/LinLTLL12
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Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li:
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. ASP-DAC 2012: 437-442
[c7]
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Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh:
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD 2012: 713-719
[c6]
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Wen-Hao Liu, Yih-Lang Li:
Optimizing the antenna area and separators in layer assignment of multi-layer global routing. ISPD 2012: 137-144
2011
[c5]
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Wen-Hao Liu, Yih-Lang Li:
Negotiation-based layer assignment for via count and via overflow minimization. ASP-DAC 2011: 539-544
[c4]
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Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao:
High-quality global routing for multiple dynamic supply voltage designs. ICCAD 2011: 263-269
2010
[c3]
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  - conf/aspdac/LiuLC10
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Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen:
Minimizing clock latency range in robust clock tree synthesis. ASP-DAC 2010: 389-394
[c2]
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Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing. DAC 2010: 200-205
2009
[c1]
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  - conf/aspdac/DaiLL09
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Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. ASP-DAC 2009: 570-575

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