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ORCIDJennifer Dworak
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2020 – today
- 2024
[c60]Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Dual Use Circuitry for Early Failure Warning and Test. ISQED 2024: 1-8- 2023
- [j12]Hui Jiang
, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas:
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. J. Electron. Test. 39(2): 227-243 (2023) - [c59]Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Harvesting Wasted Clock Cycles for Efficient Online Testing. ETS 2023: 1-6 - 2021
- [j11]Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch:
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. IEEE Trans. Emerg. Top. Comput. 9(2): 774-786 (2021) - [c58]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar:
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC 2021: 319-323 - 2020
- [j10]Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak:
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift. IEEE Des. Test 37(4): 14-20 (2020) - [c57]David Brauchler, Jennifer Dworak:
Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks. ITC 2020: 1-10
2010 – 2019
- 2019
- [j9]Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35(6): 887-900 (2019) - [c56]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Test Architecture for Fine Grained Capture Power Reduction. ICECS 2019: 558-561 - [c55]Alfred L. Crouch, Peter L. Levin, Jennifer Dworak, Lakshmi Ramakrishnan, Yuhe Xia, Chi Zhang, Daniel Engels, Gary Evans, Ping Gui, Scott McWilliams, Saurabh Gupta, Franco Stellari, Naigang Wang, Peilin Song:
Innovate Practices on CyberSecurity of Hardware Semiconductor Devices. VTS 2019: 1 - [c54]Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak:
A Novel Graph Coloring Based Solution for Low-Power Scan Shift. VTS 2019: 1-6 - 2018
- [c53]Senwen Kan, Jennifer Dworak:
Can Soft Errors be Handled Securely? ISVLSI 2018: 124-129 - [c52]Senwen Kan, Jennifer Dworak:
IJTAG Integrity Checking with Chained Hashing. ITC 2018: 1-10 - [c51]Hui Jiang, Fanchen Zhang, Yi Sun, Jennifer Dworak:
One more time! Increasing fault detection with scan shift capture. NATW 2018: 1-7 - [c50]Saurabh Gupta, Jae Wu, Jennifer Dworak:
Efficient parallel testing: A configurable and scalable broadcast network design using IJTAG. VTS 2018: 1-6 - [c49]Qutaiba Khasawneh, Jennifer Dworak, Ping Gui, Benjamin Williams, Alan C. Elliott, Anand Muthaiah:
Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment. VTS 2018: 1-6 - 2017
- [c48]Senwen Kan, Jennifer Dworak:
Systematic Test Generation for Secure Hardware Supported Virtualization. DASC/PiCom/DataCom/CyberSciTech 2017: 550-556 - [c47]Saurabh Gupta, Al Crouch, Jennifer Dworak, Daniel Engels:
Increasing IJTAG bandwidth and managing security through parallel locking-SIBs. ITC 2017: 1-10 - [c46]Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch:
Detecting a trojan die in 3D stacked integrated circuits. NATW 2017: 1-6 - [c45]Saurabh Gupta, Jennifer Dworak, Daniel Engels, Al Crouch:
Mitigating simple power analysis attacks on LSIB key logic. NATW 2017: 1-6 - 2016
- [c44]Senwen Kan, Jennifer Dworak, James George Dunham:
Echeloned IJTAG data protection. AsianHOST 2016: 1-6 - [c43]Fanchen Zhang, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg, Jennifer Dworak:
Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture. ITC 2016: 1-10 - [c42]Senwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak:
A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor. MTV 2016: 19-24 - [c41]Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter:
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW 2016: 46-52 - 2015
- [j8]Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan:
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 849-861 (2015) - [c40]Senwen Kan, Marco Ottavi, Jennifer Dworak:
Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. DFTS 2015: 119-122 - [c39]Tassanee Payakapan, Senwen Kan, Ken Pham, Kathy Yang, Jean-Francois Cote, Martin Keim, Jennifer Dworak:
A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor. ITC 2015: 1-10 - [c38]Jennifer Dworak, Ping Gui, Qutaiba Khasawneh:
An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices. NATW 2015: 33-38 - [c37]Jennifer Dworak, Al Crouch:
A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard. VTS 2015: 1-4 - 2014
- [c36]Adam Zygmontowicz, Jennifer Dworak, Al Crouch, John C. Potter:
Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network. DATE 2014: 1-6 - [c35]Senwen Kan, Jennifer Dworak:
Triggering Trojans in SRAM circuits with X-propagation. DFT 2014: 1-8 - [c34]Jennifer Dworak, Zoe Conroy, Alfred L. Crouch, John C. Potter:
Board security enhancement using new locking SIB-based architectures. ITC 2014: 1-10 - [c33]Fanchen Zhang, Micah Thornton, Jennifer Dworak:
When Optimized N-Detect Test Sets are Biased: An Investigation of Cell-Aware-Type Faults and N-Detect Stuck-At ATPG. NATW 2014: 32-39 - [c32]Jennifer Dworak:
Special session 4A: Elevator talks. VTS 2014: 1 - 2013
- [j7]Alfred L. Crouch, John C. Potter, Ajay Khoche, Jennifer Dworak:
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System. IEEE Des. Test 30(5): 6-14 (2013) - [j6]Yiwen Shi, Jennifer Dworak:
A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects. J. Electron. Test. 29(3): 275-288 (2013) - [c31]Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS 2013: 243-248 - [c30]Mitchell A. Thornton, Jennifer Dworak:
Ternary Logic Network Justification Using Transfer Matrices. ISMVL 2013: 310-315 - [c29]Jennifer Dworak, Al Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton:
Don't forget to lock your SIB: Hiding instruments using P16871. ITC 2013: 1-10 - [c28]Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1 - 2012
- [j5]Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak:
NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 809-813 (2012) - [j4]Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar:
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18(1): 14:1-14:19 (2012) - 2011
- [c27]Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar:
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS 2011: 211 - [c26]Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak:
Partial state monitoring for fault detection estimation. ITC 2011: 1-10 - [c25]Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246 - 2010
- [j3]Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 788-801 (2010) - [j2]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1110-1120 (2010) - [c24]Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel:
NIM- a noise index model to estimate delay discrepancies between silicon and simulation. DATE 2010: 1373-1376 - [c23]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134 - [c22]Yiwen Shi, Wan-Chan Hu, Jennifer Dworak:
Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects. VTS 2010: 319-324
2000 – 2009
- 2009
- [c21]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Detecting errors using multi-cycle invariance information. DATE 2009: 791-796 - [c20]Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88 - 2008
- [c19]Yiwen Shi, Kellie DiPalma, Jennifer Dworak:
Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization. DFT 2008: 403-411 - [c18]Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar:
Using Implications for Online Error Detection. ITC 2008: 1-10 - [c17]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
Reducing Scan Shift Power at RTL. VTS 2008: 139-146 - 2007
- [c16]Jennifer Dworak:
Which defects are most critical? optimizing test sets to minimize failures due to test escapes. ITC 2007: 1-10 - [c15]Jennifer Dworak:
An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting. VTS 2007: 205-210 - 2006
- [c14]Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss:
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. DAC 2006: 705-708 - 2005
- [c13]Jennifer Dworak:
An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects. MTV 2005: 48-54 - 2004
- [c12]Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer:
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. DATE 2004: 1066-1071 - [c11]Jennifer Dworak, James Wingfield, M. Ray Mercer:
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. DFT 2004: 460-468 - [c10]Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer:
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. VTS 2004: 9-15 - 2003
- [c9]James Wingfield, Jennifer Dworak, M. Ray Mercer:
Function-Based Dynamic Compaction and its Impact on Test Set Sizes. DFT 2003: 167-174 - 2002
- [c8]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 - [c7]Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer:
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. DATE 2002: 94-99 - [c6]Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT 2002: 177-185 - [c5]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 - 2001
- [j1]Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang:
Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Des. Test Comput. 18(1): 31-41 (2001) - 2000
- [c4]Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151- - [c3]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC 2000: 930-939
1990 – 1999
- 1999
- [c2]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC 1999: 1031-1037 - [c1]Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer:
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS 1999: 268-274
Coauthor Index
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