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John Wawrzynek
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- affiliation: University of California, Berkeley, USA
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2020 – today
- 2022
- [c79]Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao:
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. ISPASS 2022: 277-287 - 2021
- [c78]Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. FCCM 2021: 50-59 - [c77]Qijing Huang, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek:
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. FPGA 2021: 206-216 - [c76]Qijing Huang, Aravind Kalaiah, Minwoo Kang, James Demmel, Grace Dinh, John Wawrzynek, Thomas Norell, Yakun Sophia Shao:
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. ISCA 2021: 554-566 - [i14]Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference. CoRR abs/2104.12766 (2021) - [i13]Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao:
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. CoRR abs/2105.01898 (2021) - 2020
- [c75]Ameer Haj-Ali, Qijing (Jenny) Huang, William S. Moses, John Xiang, Krste Asanovic, John Wawrzynek, Ion Stoica:
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. MLSys 2020 - [c74]Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek:
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) 2020: 113-131 - [i12]Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek:
Algorithm-hardware Co-design for Deformable Convolution. CoRR abs/2002.08357 (2020) - [i11]Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. CoRR abs/2003.00671 (2020) - [i10]Ameer Haj-Ali, Hasan Genc, Qijing Huang, William S. Moses, John Wawrzynek, Krste Asanovic, Ion Stoica:
ProTuner: Tuning Programs with Monte Carlo Tree Search. CoRR abs/2005.13685 (2020) - [i9]Zhen Dong, Dequan Wang, Qijing Huang, Yizhao Gao, Yaohui Cai, Bichen Wu, Kurt Keutzer, John Wawrzynek:
CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. CoRR abs/2006.08357 (2020)
2010 – 2019
- 2019
- [j25]Guohao Dai
, Tianhao Huang, Yu Wang
, Huazhong Yang
, John Wawrzynek:
HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing. IEEE Trans. Computers 68(8): 1131-1146 (2019) - [c73]Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. ASP-DAC 2019: 120-126 - [c72]Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. FCCM 2019: 308 - [c71]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma
, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA 2019: 23-32 - [c70]Qijing Huang, Christopher Yarp
, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma
, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek:
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. ICCAD 2019: 1-8 - [c69]Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek:
Algorithm-hardware Co-design for Deformable Convolution. EMC2@NeurIPS 2019: 48-51 - [c68]James C. Martin, Robert W. Brodersen, John Wawrzynek:
Antenna Array Geometries for Directional Wireless Networks. WCNC 2019: 1-6 - [i8]Ameer Haj Ali, Qijing Huang, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. CoRR abs/1901.04615 (2019) - 2018
- [c67]Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. FCCM 2018: 208 - [c66]James C. Martin, Robert W. Brodersen, John Wawrzynek:
Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave. PIMRC 2018: 1-7 - [c65]Ben Zhang, Xin Jin, Sylvia Ratnasamy, John Wawrzynek, Edward A. Lee:
AWStream: adaptive wide-area streaming analytics. SIGCOMM 2018: 236-252 - [i7]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR abs/1811.08634 (2018) - 2017
- [c64]Simon Scott, John Wawrzynek:
Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging. EUSIPCO 2017: 1314-1318 - [c63]Hayden Kwok-Hay So, John Wawrzynek:
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. FPGA 2017: 1 - [c62]Shaoyi Cheng, Qijing Huang, John Wawrzynek:
Synthesis of program binaries into FPGA accelerators with runtime dependence validation. FPT 2017: 96-103 - [c61]Filip Lemic
, Vlado Handziski, Mladen Miksa, Jan M. Rabaey, John Wawrzynek, Adam Wolisz:
Selection and Aggregation of Location Information Provisioning Services. ICCCN 2017: 1-9 - [c60]Filip Lemic
, Vlado Handziski, Ivan Azcarate, John Wawrzynek, Jan M. Rabaey, Adam Wolisz:
SLSR: A flexible middleware localization service architecture. IPIN 2017: 1-8 - [i6]Hayden Kwok-Hay So, John Wawrzynek:
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). CoRR abs/1704.08802 (2017) - 2016
- [j24]Nitesh Mor, Ben Zhang, John Kolb, Douglas S. Chan, Nikhil Goyal, Nicholas Sun, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz:
Toward a Global Data Infrastructure. IEEE Internet Comput. 20(3): 54-62 (2016) - [c59]Hayden Kwok-Hay So
, John Wawrzynek:
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. FPGA 2016: 1 - [c58]Shaoyi Cheng, John Wawrzynek:
Synthesis of statically analyzable accelerator networks from sequential programs. ICCAD 2016: 126 - [c57]Filip Lemic
, Vlado Handziski, Nitesh Mor, Jan M. Rabaey, John Wawrzynek, Adam Wolisz:
Toward standardized localization service. IPIN 2016: 1-8 - [c56]Filip Lemic
, James C. Martin, Christopher Yarp
, Douglas S. Chan, Vlado Handziski, Robert W. Brodersen, Gerhard P. Fettweis, Adam Wolisz, John Wawrzynek:
Localization as a feature of mmWave communication. IWCMC 2016: 1033-1038 - [i5]Hayden Kwok-Hay So, John Wawrzynek:
Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). CoRR abs/1605.08149 (2016) - [i4]Shaoyi Cheng, John Wawrzynek:
High Level Synthesis with a Dataflow Architectural Template. CoRR abs/1606.06451 (2016) - 2015
- [j23]Mingjie Lin, Shaoyi Cheng, Ronald F. DeMara
, John Wawrzynek:
ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism. Microprocess. Microsystems 39(7): 553-564 (2015) - [c55]Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz:
The Cloud is Not Enough: Saving IoT from the Cloud. HotCloud 2015 - [c54]Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz:
The Cloud is Not Enough: Saving IoT from the Cloud. HotStorage 2015 - 2014
- [j22]Edward A. Lee, Björn Hartmann, John Kubiatowicz, Tajana Simunic Rosing, John Wawrzynek, David Wessel, Jan M. Rabaey, Kris Pister, Alberto L. Sangiovanni-Vincentelli
, Sanjit A. Seshia, David T. Blaauw, Prabal Dutta, Kevin Fu, Carlos Guestrin, Ben Taskar, Roozbeh Jafari
, Douglas L. Jones, Vijay Kumar, Rahul Mangharam, George J. Pappas
, Richard M. Murray
, Anthony Rowe:
The Swarm at the Edge of the Cloud. IEEE Des. Test 31(3): 8-20 (2014) - [c53]Shaoyi Cheng, John Wawrzynek:
Architectural synthesis of computational pipelines with decoupled memory access. FPT 2014: 83-90 - 2013
- [c52]Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek:
Reconfigurable computing in the era of post-silicon scaling [panel discussion]. FCCM 2013 - [c51]Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
Extracting memory-level parallelism through reconfigurable hardware traces. ReConFig 2013: 1-8 - 2012
- [j21]Ilia A. Lebedev
, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek:
Exploring Many-Core Design Templates for FPGAs and ASICs. Int. J. Reconfigurable Comput. 2012: 439141:1-439141:15 (2012) - [j20]Mingjie Lin, Yu Bai, John Wawrzynek:
Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience. J. Electr. Comput. Eng. 2012: 593532:1-593532:12 (2012) - [c50]Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225 - [c49]Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek:
Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. FCCM 2012: 157-160 - 2011
- [c48]John Wawrzynek:
Advances and challenges of computing with FPGAs. CICC 2011: 1 - [c47]John Wawrzynek:
Should the academic community launch an open-source FPGA device and tools effort?: evening panel. FPGA 2011: 3-4 - [c46]Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek:
Bridging the GPGPU-FPGA efficiency gap. FPGA 2011: 119-122 - [c45]Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
Using many-core architectural templates for FPGA-based computing (abstract only). FPGA 2011: 281 - [c44]Mingjie Lin, Yu Bai, John Wawrzynek:
Discriminatively Fortified Computing with Reconfigurable Digital Fabric. HASE 2011: 112-119 - [e2]John Wawrzynek, Katherine Compton:
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. ACM 2011, ISBN 978-1-4503-0554-9 [contents] - [i3]John Lazzaro, John Wawrzynek:
RTP Payload Format for MIDI. RFC 6295: 1-171 (2011) - 2010
- [j19]Mingjie Lin, John Wawrzynek, Abbas El Gamal:
Exploring FPGA Routing Architecture Stochastically. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1509-1522 (2010) - [j18]Mingjie Lin, John Wawrzynek:
Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1858-1869 (2010) - [c43]Mingjie Lin, Ilia A. Lebedev, John Wawrzynek:
High-throughput bayesian computing machine with reconfigurable hardware. FPGA 2010: 73-82 - [c42]Mingjie Lin, Ilia A. Lebedev, John Wawrzynek:
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. FPL 2010: 458-463 - [c41]Narges Bani Asadi, Christopher W. Fletcher, Greg Gibeling, John Wawrzynek, Wing H. Wong, Garry P. Nolan:
ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs. ICS 2010: 83-94 - [c40]Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James C. Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek:
MARC: A Many-Core Approach to Reconfigurable Computing. ReConFig 2010: 7-12 - [c39]Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. ReConFig 2010: 103-108 - [e1]Peter Y. K. Cheung, John Wawrzynek:
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. ACM 2010, ISBN 978-1-60558-911-4 [contents]
2000 – 2009
- 2009
- [j17]Krste Asanovic, Rastislav Bodík, James Demmel, Tony M. Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick:
A view of the parallel computing landscape. Commun. ACM 52(10): 56-67 (2009) - [c38]Yury Markovsky, Yatish Patel, John Wawrzynek:
Using adaptive routing to compensate for performance heterogeneity. NOCS 2009: 12-21 - [c37]Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf
, John Wawrzynek, Samuel Williams:
A design methodology for domain-optimized power-efficient supercomputing. SC 2009 - 2008
- [j16]Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek:
Workloads of the Future. IEEE Des. Test Comput. 25(4): 358-365 (2008) - 2007
- [j15]John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007) - [c36]John Wawrzynek:
Adventures with a Reconfigurable Research Platform. FPL 2007: 3 - [c35]Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz:
RAMP Blue: A Message-Passing Manycore System in FPGAs. FPL 2007: 54-61 - 2006
- [j14]André DeHon, Randy Huang, John Wawrzynek:
Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems 30(6): 301-318 (2006) - [j13]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek:
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30(6): 334-354 (2006) - [c34]David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek:
Research accelerator for multiple processors. Hot Chips Symposium 2006: 1-42 - [i2]John Lazzaro, John Wawrzynek:
RTP Payload Format for MIDI. RFC 4695: 1-169 (2006) - [i1]John Lazzaro, John Wawrzynek:
An Implementation Guide for RTP MIDI. RFC 4696: 1-38 (2006) - 2005
- [j12]Chen Chang, John Wawrzynek, Robert W. Brodersen:
BEE2: A High-End Reconfigurable Computing System. IEEE Des. Test Comput. 22(2): 114-125 (2005) - [c33]Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen:
The Design And Application Of A High-End Reconfigurable Computing System. ERSA 2005: 129-136 - [c32]Zohair Hyder, John Wawrzynek:
Defect Tolerance in Multiple-FPGA Systems. FPL 2005: 247-254 - 2004
- [c31]Nicholas Weaver, John R. Hauser, John Wawrzynek:
The SFRA: a corner-turn FPGA architecture. FPGA 2004: 3-12 - 2003
- [j11]John Wawrzynek, Keith Diefendorff:
Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. IEEE Micro 23(2): 8-11 (2003) - [c30]Randy Huang, John Wawrzynek, André DeHon:
Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87 - [c29]Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek:
Post-placement C-slow retiming for the xilinx virtex FPGA. FPGA 2003: 185-194 - [c28]Joseph Yeh, John Wawrzynek:
Quality based compute-resource allocation in real-time signal processing. ICASSP (2) 2003: 545-548 - 2002
- [c27]André DeHon, Randy Huang, John Wawrzynek:
Hardware-Assisted Fast Routing. FCCM 2002: 205- - [c26]Nicholas Weaver, John Wawrzynek:
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. FCCM 2002: 303- - [c25]Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205 - 2001
- [c24]John Lazzaro, John Wawrzynek:
A case for network musical performance. NOSSDAV 2001: 157-166 - 2000
- [j10]Timothy J. Callahan, John R. Hauser, John Wawrzynek:
The Garp Architecture and C Compiler. Computer 33(4): 62-69 (2000) - [c23]Nicholas Weaver, John Wawrzynek:
A Comparison of the AES Candidates Amenability to FPGA Implementation. AES Candidate Conference 2000: 28-39 - [c22]Timothy J. Callahan, John Wawrzynek:
Adapting software pipelining for reconfigurable computing. CASES 2000: 57-64 - [c21]Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614
1990 – 1999
- 1999
- [j9]Norman P. Jouppi, John Wawrzynek:
Real products, real technology Guest Editor's Introduction]. IEEE Micro 19(2): 10-11 (1999) - [j8]John Lazzaro, John Wawrzynek:
JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. Neural Comput. 11(1): 267-296 (1999) - [c20]André DeHon, John Wawrzynek:
Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC 1999: 610-615 - [c19]William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134 - [c18]Todd D. Hodes, John R. Hauser, John Wawrzynek, Adrian Freed, David Wessel:
A fixed-point recursive digital oscillator for additive synthesis of audio. ICASSP 1999: 993-996 - 1998
- [c17]Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek:
Object Oriented Circuit-Generators in Java. FCCM 1998: 158-166 - [c16]Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek:
Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA 1998: 123-132 - [c15]Timothy J. Callahan, John Wawrzynek:
Instruction-Level Parallelism for Reconfigurable Computing. FPL 1998: 248-257 - 1997
- [j7]John Lazzaro, John Wawrzynek, Richard P. Lippmann:
A micropower analog circuit implementation of hidden Markov model state decoding. IEEE J. Solid State Circuits 32(8): 1200-1209 (1997) - [c14]John R. Hauser, John Wawrzynek:
Garp: a MIPS processor with a reconfigurable coprocessor. FCCM 1997: 12-21 - [c13]Timothy J. Callahan, John Wawrzynek:
Datapath-oriented FPGA mapping and placement for configurable computing. FCCM 1997: 234-235 - 1996
- [j6]John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan:
Spert-II: A Vector Microprocessor System. Computer 29(3): 79-86 (1996) - [c12]John Lazzaro, John Wawrzynek, Richard Lippmann:
A Micropower Analog VLSI HMM State Decoder for Wordspotting. NIPS 1996: 727-733 - 1995
- [c11]John Lazzaro, John Wawrzynek:
A multi-sender asynchronous extension to the AER protocol. ARVLSI 1995: 158-171 - [c10]John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan:
SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. NIPS 1995: 619-625 - [c9]John Lazzaro, John Wawrzynek:
Silicon Models for Auditory Scene Analysis. NIPS 1995: 699-705 - 1994
- [j5]John Lazzaro, John Wawrzynek, Alan Kramer:
Systems technologies for silicon auditory models. IEEE Micro 14(3): 7-15 (1994) - 1993
- [j4]Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek:
Designing A Connectionist Network Supercomputer. Int. J. Neural Syst. 4(4): 317-326 (1993) - [j3]John Wawrzynek, Krste Asanovic, Nelson Morgan:
The design of a neuro-microprocessor. IEEE Trans. Neural Networks 4(3): 394-399 (1993) - [j2]John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie:
Silicon auditory processors as computer peripherals. IEEE Trans. Neural Networks 4(3): 523-528 (1993) - [j1]Krste Asanovic, Nelson Morgan, John Wawrzynek:
Using simulations of reduced precision arithmetic to design a neuro-microprocessor. J. VLSI Signal Process. 6(1): 33-44 (1993) - 1992
- [c8]Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek:
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. ASAP 1992: 178-190 - [c7]John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie:
Silicon Auditory Processors as Computer Peripherals. NIPS 1992: 820-827 - 1991
- [c6]David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek:
Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. ASPLOS 1991: 164-175 - [c5]Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya:
A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC 1991: 727-731 - 1990
- [c4]Sam Pointer, John Wawrzynek, David Wessel:
A Multimedia Digital Signal Processing Tutoring System. ICMC 1990 - [c3]John Wawrzynek, Thorsten von Eicken:
VLSI Parallel Processing for Musical Sound Synthesis. ICMC 1990
1980 – 1989
- 1989
- [c2]David Wessel, Richard Felciano, Adrian Freed, John Wawrzynek:
The Center for New Music and Audio Technologies. ICMC 1989 - 1984
- [c1]