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2020 – today
- 2025
[j16]Monodeep Kar
, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. IEEE J. Solid State Circuits 60(1): 49-64 (2025)- 2024
- [j15]Sanchari Sen, Shubham Jain, Sarada Krithivasan, Swagath Venkataramani, Vijayalakshmi Srinivasan:
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU. IEEE Micro 44(6): 63-72 (2024) - [c51]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256 - 2022
- [j14]Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - [j13]Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan:
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators. ACM Trans. Embed. Comput. Syst. 21(6): 86:1-86:29 (2022) - [c50]Naigang Wang, Chi-Chun (Charlie) Liu, Swagath Venkataramani, Sanchari Sen, Chia-Yu Chen, Kaoutar El Maghraoui, Vijayalakshmi Srinivasan, Leland Chang:
Deep Compression of Pre-trained Transformer Models. NeurIPS 2022 - 2021
- [c49]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c48]Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan:
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. ISPASS 2021: 240-242 - [c47]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - [i4]Chia-Yu Chen, Jiamin Ni, Songtao Lu, Xiaodong Cui, Pin-Yu Chen, Xiao Sun, Naigang Wang, Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Zhang, Kailash Gopalakrishnan:
ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training. CoRR abs/2104.11125 (2021) - 2020
- [j12]Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan:
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [c46]Chia-Yu Chen, Jiamin Ni, Songtao Lu, Xiaodong Cui, Pin-Yu Chen, Xiao Sun, Naigang Wang, Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Zhang, Kailash Gopalakrishnan:
ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training. NeurIPS 2020 - [c45]Xiao Sun, Naigang Wang, Chia-Yu Chen, Jiamin Ni, Ankur Agrawal, Xiaodong Cui, Swagath Venkataramani, Kaoutar El Maghraoui, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan:
Ultra-Low Precision 4-bit Training of Deep Neural Networks. NeurIPS 2020 - [c44]Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j11]Swagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Wei Wang, Jintao Zhang, Marcel Schaal, Mauricio J. Serrano, Kazuaki Ishizaki, Hiroshi Inoue, Eri Ogawa, Moriyoshi Ohara, Leland Chang, Kailash Gopalakrishnan:
DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator. IEEE Micro 39(5): 102-111 (2019) - [c43]Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Swagath Venkataramani, Jungwook Choi, Wei Wang, Vijayalakshmi Srinivasan, Moriyoshi Ohara, Kailash Gopalakrishnan:
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel. COOL CHIPS 2019: 1-3 - [c42]Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Kailash Gopalakrishnan, Leland Chang:
BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks. DAC 2019: 201 - [c41]Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Philip Heidelberger, Leland Chang, Kailash Gopalakrishnan:
Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems. HiPC 2019: 225-234 - [c40]Sungho Shin, Youngmin Jo, Jungwook Choi, Swagath Venkataramani, Vijayalakshmi Srinivasan, Wonyong Sung:
Workload-aware Automatic Parallelization for Multi-GPU DNN Training. ICASSP 2019: 1453-1457 - [c39]Swagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Leland Chang:
Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators. IISWC 2019: 257-262 - [c38]Jungwook Choi, Swagath Venkataramani, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Zhuo Wang, Pierce Chuang:
Accurate and Efficient 2-bit Quantized Neural Networks. SysML 2019 - [c37]Xiao Sun, Jungwook Choi, Chia-Yu Chen, Naigang Wang, Swagath Venkataramani, Vijayalakshmi Srinivasan, Xiaodong Cui, Wei Zhang, Kailash Gopalakrishnan:
Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks. NeurIPS 2019: 4901-4910 - 2018
- [c36]Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Pierce Chuang, Leland Chang:
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. DAC 2018: 38:1-38:6 - [c35]Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Viji Srinivasan, Swagath Venkataramani:
Exploiting approximate computing for deep learning acceleration. DATE 2018: 821-826 - [c34]Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Kailash Gopalakrishnan, Leland Chang:
Taming the beast: Programming Peta-FLOP class Deep Learning Systems. ISLPED 2018: 18:1 - [c33]Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED 2018: 35:1-35:2 - [c32]Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits 2018: 35-36 - [i3]Jungwook Choi, Zhuo Wang, Swagath Venkataramani, Pierce I-Jen Chuang, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan:
PACT: Parameterized Clipping Activation for Quantized Neural Networks. CoRR abs/1805.06085 (2018) - [i2]Jungwook Choi, Pierce I-Jen Chuang, Zhuo Wang, Swagath Venkataramani, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan:
Bridging the Accuracy Gap for 2-bit Quantized Neural Networks (QNN). CoRR abs/1807.06964 (2018) - [i1]Sungho Shin, Youngmin Jo, Jungwook Choi, Swagath Venkataramani, Vijayalakshmi Srinivasan, Wonyong Sung:
Workload-aware Automatic Parallelization for Multi-GPU DNN Training. CoRR abs/1811.01532 (2018) - 2017
- [j10]Vijayalakshmi Srinivasan, Yunquan Zhang:
Special Issue on Network and Parallel Computing. Int. J. Parallel Program. 45(1): 1-3 (2017) - [c31]Swagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Leland Chang:
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators. PACT 2017: 146-147 - [c30]Ankur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang:
Accelerator Design for Deep Learning Training: Extended Abstract: Invited. DAC 2017: 57:1-57:2 - [c29]Snehasish Kumar, Nick Sumner, Vijayalakshmi Srinivasan, Steve Margerm, Arrvindh Shriraman:
Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs. HPCA 2017: 565-576 - 2016
- [c28]Ankur Agrawal, Jungwook Choi, Kailash Gopalakrishnan, Suyog Gupta, Ravi Nair, Jinwook Oh, Daniel A. Prener, Sunil Shukla, Vijayalakshmi Srinivasan, Zehra Sura:
Approximate computing: Challenges and opportunities. ICRC 2016: 1-8 - [c27]Snehasish Kumar, Vijayalakshmi Srinivasan, Amirali Sharifian, Nick Sumner, Arrvindh Shriraman:
Peruse and Profit: Estimating the Accelerability of Loops. ICS 2016: 21:1-21:13 - [c26]Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks:
Co-designing accelerators and SoC interfaces using gem5-Aladdin. MICRO 2016: 48:1-48:12 - 2015
- [c25]Snehasish Kumar, Naveen Vedula, Arrvindh Shriraman, Vijayalakshmi Srinivasan:
DASX: Hardware Accelerator for Software Data Structures. ICS 2015: 361-372 - [c24]Islam Atta, Xin Tong, Vijayalakshmi Srinivasan, Ioana Baldini, Andreas Moshovos:
Self-contained, accurate precomputation prefetching. MICRO 2015: 153-165 - 2014
- [j9]Seth H. Pugsley, Jeffrey Jestes, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li:
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. IEEE Micro 34(4): 44-52 (2014) - [c23]Snehasish Kumar, Arrvindh Shriraman, Vijayalakshmi Srinivasan, Dan Lin, Jordon Phillips:
SQRL: hardware accelerator for collecting software data structures. PACT 2014: 475-476 - [c22]Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li:
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. ISPASS 2014: 190-200 - 2013
- [c21]Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, Andreas Moshovos:
RECAP: A region-based cure for the common cold (cache). HPCA 2013: 83-94 - 2012
- [c20]Jason Zebchuk, Harold W. Cain, Vijayalakshmi Srinivasan, Andreas Moshovos:
ReCaP: a region-based cure for the common cold cache. PACT 2012: 443-444 - [c19]Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan:
Efficient scrub mechanisms for error-prone emerging memories. HPCA 2012: 15-26 - [c18]Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, Daniel A. Prener:
Programming with relaxed synchronization. RACES@SPLASH 2012: 41-50 - [e1]Rajeev Balasubramonian, Vijayalakshmi Srinivasan:
2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1143-4 [contents] - 2011
- [j8]Andrew B. Kahng, Vijayalakshmi Srinivasan:
Big Chips. IEEE Micro 31(4): 3-5 (2011) - [c17]Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan:
SPATL: Honey, I Shrunk the Coherence Directory. PACT 2011: 33-44 - 2010
- [c16]Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee:
SAFER: Stuck-At-Fault Error Recovery for Memories. MICRO 2010: 115-124
2000 – 2009
- 2009
- [c15]Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers:
Scalable high performance main memory system using phase-change memory technology. ISCA 2009: 24-33 - [c14]Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Bülent Abali:
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. MICRO 2009: 14-23 - [c13]Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos:
A tagless coherence directory. MICRO 2009: 423-434 - 2008
- [j7]Allan Hartstein, Vijayalakshmi Srinivasan, Thomas R. Puzak, Philip G. Emma:
On the Nature of Cache Miss Behavior: Is It √2? J. Instr. Level Parallelism 10 (2008) - [j6]Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Vijayalakshmi Srinivasan, Arthur Nadas:
Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy. J. Instr. Level Parallelism 10 (2008) - 2007
- [c12]Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Jim Mitchell:
An analysis of the effects of miss clustering on the cost of a cache miss. Conf. Computing Frontiers 2007: 3-12 - [c11]Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Arthur Nadas:
Pipeline spectroscopy. Experimental Computer Science 2007: 15 - [c10]Thomas R. Puzak, Allan Hartstein, Viji Srinivasan, Philip G. Emma, Arthur Nadas:
Pipeline spectroscopy. SIGMETRICS 2007: 351-352 - 2006
- [c9]Allan Hartstein, Viji Srinivasan, Thomas R. Puzak, Philip G. Emma:
Cache miss behavior: is it sqrt(2)? Conf. Computing Frontiers 2006: 313-320 - 2005
- [j5]Philip G. Emma, Allan Hartstein, Thomas R. Puzak, Viji Srinivasan:
Exploring the limits of prefetching. IBM J. Res. Dev. 49(1): 127-144 (2005) - [c8]Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan:
When prefetching improves/degrades performance. Conf. Computing Frontiers 2005: 342-352 - 2004
- [j4]Viji Srinivasan, Edward S. Davidson, Gary S. Tyson:
A Prefetch Taxonomy. IEEE Trans. Computers 53(2): 126-140 (2004) - [j3]Victor V. Zyuban, David M. Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma:
Integrated Analysis of Power and Performance for Pipelined Microprocessors. IEEE Trans. Computers 53(8): 1004-1016 (2004) - [c7]Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose:
Microarchitectural techniques for power gating of execution units. ISLPED 2004: 32-37 - 2003
- [j2]David M. Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield:
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM J. Res. Dev. 47(5-6): 653-670 (2003) - [c6]Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu:
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. PACS 2003: 180-195 - 2002
- [c5]Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma:
Optimizing pipelines for power and performance. MICRO 2002: 333-344 - [c4]Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas:
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS 2002: 1-17 - 2001
- [b1]Vijayalakshmi Srinivasan:
Hardware solutions to reduce effective memory access time. University of Michigan, USA, 2001 - [c3]Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak:
Branch History Guided Instruction Prefetching. HPCA 2001: 291-300
1990 – 1999
- 1999
- [j1]Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999) - 1998
- [c2]Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
Evaluating the performance of active cache management schemes. ICCD 1998: 368-375 - 1997
- [c1]Sucheta Chodnekar, Viji Srinivasan, Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das:
Towards a Communication Characterization Methodology for Parallel Applications. HPCA 1997: 310-319
Coauthor Index
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