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ORCIDJaejin Park
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2010 – 2019
- 2017
[j6]Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 655-659 (2017)- 2016
- [c13]Vadim Ivanov, Jaejin Park:
Session 12 overview: Efficient Power Conversion. ISSCC 2016: 216-217 - 2014
- [j5]Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits 49(3): 657-672 (2014) - [c12]Jenlung Liu, Tae-Kwang Jang
, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park:
15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ISSCC 2014: 268-269 - 2013
- [c11]Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim:
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. ICCAD 2013: 486-493 - [c10]Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC 2013: 250-251 - [c9]Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park:
A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. ISSCC 2013: 254-255 - 2012
- [c8]Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. ISSCC 2012: 240-242 - [c7]Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho:
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC 2012: 336-337 - 2011
- [c6]Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park:
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. A-SSCC 2011: 337-340
2000 – 2009
- 2008
- [j4]Jongsun Park, Jaejin Park, Suwang Jang, Seryun Kim, Sunghyung Kong, Jaeyoung Choi, Kyohun Ahn, Juhyeon Kim, Seungmin Lee, Sunggon Kim, Bongsoo Park, Kyongyong Jung, Soonok Kim, Seogchan Kang, Yong-Hwan Lee:
FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors. Bioinform. 24(7): 1024-1025 (2008) - [j3]Jongsun Park, Bongsoo Park, Kyongyong Jung, Suwang Jang, Kwangyul Yu, Jaeyoung Choi, Sunghyung Kong, Jaejin Park, Seryun Kim, Hyojeong Kim, Soonok Kim, Jihyun F. Kim, Jaime E. Blair, Kwangwon Lee, Seogchan Kang, Yong-Hwan Lee:
CFGP: a web-based, comparative fungal genomics platform. Nucleic Acids Res. 36(Database-Issue): 562-571 (2008) - 2007
- [c5]Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue:
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. CICC 2007: 281-284 - 2005
- [c4]Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue:
A low-power, 20-Gb/s continuous-time adaptive passive equalizer. ISCAS (2) 2005: 920-923 - [c3]Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue:
A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. ISCAS (2) 2005: 1162-1165 - 2000
- [c2]Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo, Philip Chung:
A 1 mW 10-bit 500KSPS SAR A/D converter. ISCAS 2000: 581-584
1990 – 1999
- 1999
- [j2]Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song:
A 5-MHz IF digital FM demodulator. IEEE J. Solid State Circuits 34(1): 3-11 (1999) - 1995
- [j1]Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE J. Solid State Circuits 30(8): 940-943 (1995) - 1994
- [c1]Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. ISCAS 1994: 319-322
Coauthor Index
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