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ORCIDBinod Kumar 0001
Person information
- affiliation: Indian Institute of Technology Jodhpur, India
Other persons with the same name
- Binod Kumar — disambiguation page
- Binod Kumar 0002 — Higher College of Technology, Muscat, Oman
- Binod Kumar 0003 — Indian Institute of Technology, Kharagpur, India
- Binod Kumar 0004 — Ambedkar Institute of Technology, Delhi, India
- Binod Kumar 0005 — Saurashtra University, Rajkot, Gujarat, India
- Binod Kumar 0006 — ayawant Institute of Computer Applications, Pune, Maharashtra, India
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2020 – today
- 2023
[c27]Anshul Jain, Binod Kumar:
A Case Study on Formally Verifying an Open-source Deep Learning Accelerator Design. ATS 2023: 1-6- 2022
- [j8]Binod Kumar
, V. S. Vineesh, Puneet Nemade, Masahiro Fujita:
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5709-5721 (2022) - [c26]Utsav Jana, Sourav Banerjee, Binod Kumar, Madhu B, Shankar Umapathi, Masahiro Fujita:
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. ATS 2022: 72-77 - [c25]Sourav Banerjee, Binod Kumar, Alex Pappachen James, Jai Narayan Tripathi:
Blood Pressure Estimation from ECG Data Using XGBoost and ANN for Wearable Devices. ICECS 2022 2022: 1-4 - [c24]Jai Narayan Tripathi, Binod Kumar, Dinesh Junjariya:
Hardware Accelerator Design for Healthcare Applications: Review and Perspectives. ISCAS 2022: 1367-1371 - 2021
- [j7]V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh:
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 985-998 (2021) - [c23]Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh:
Enhancing Testbench Quality via Genetic Algorithm. MWSCAS 2021: 652-656 - 2020
- [j6]Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela:
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. ACM J. Emerg. Technol. Comput. Syst. 17(1): 5:1-5:25 (2020) - [j5]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 248-261 (2020) - [j4]Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1002-1015 (2020) - [c22]Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID 2020: 101-106 - [c21]Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde:
Analyzing Hardware Security Properties of Processors through Model Checking. VLSID 2020: 107-112 - [i1]Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela:
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. CoRR abs/2007.15248 (2020)
2010 – 2019
- 2019
- [j3]Binod Kumar, Masahiro Fujita, Virendra Singh:
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. 35(5): 655-678 (2019) - [j2]Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar:
Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications. J. Circuits Syst. Comput. 28(10): 1950171:1-1950171:14 (2019) - [c20]Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh:
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS 2019: 99-104 - [c19]Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh:
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS 2019: 123-128 - [c18]Saurabh Gangurde, Binod Kumar:
A Unified Methodology for Hardware Obfuscation and IP Watermarking. VDAT 2019: 258-271 - [c17]V. S. Vineesh, Binod Kumar, Jay Adhaduk:
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. VDAT 2019: 413-427 - [c16]Binod Kumar, Masahiro Fujita, Virendra Singh:
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID 2019: 389-394 - 2018
- [c15]Binod Kumar, Kanad Basu, Virendra Singh:
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC 2018: 1-8 - [c14]Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh:
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI 2018: 46-51 - [c13]Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita:
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSID 2018: 410-415 - 2017
- [j1]Vinay Kumar, Krishna Lal Baishnab, Binod Kumar:
A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors. J. Low Power Electron. 13(3): 490-496 (2017) - [c12]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI 2017: 191-196 - [c11]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT 2017: 59-66 - [c10]Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh:
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS 2017: 132-137 - [c9]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. LATS 2017: 1-6 - [c8]Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh:
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS 2017: 1-6 - [c7]Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita:
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT 2017: 753-766 - [c6]Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC 2017: 1-6 - [c5]Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID 2017: 147-152 - 2016
- [c4]Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh:
Performance modelling of heterogeneous ISA multicore architectures. EWDTS 2016: 1-4 - [c3]Binod Kumar, Ankit Jindal, Virendra Singh:
A trace signal selection algorithm for improved post-silicon debug. EWDTS 2016: 1-4 - [c2]Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu:
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS 2016: 1-4 - [c1]Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu:
Skip-scan: A methodology for test time reduction. VDAT 2016: 1-6
Coauthor Index
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