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2020 – today
- 2025
[j31]Shiwei Zhang
, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi:
A Transformer-Based Series-Resonance CMOS VCO. IEEE J. Solid State Circuits 60(2): 529-542 (2025)- [j30]Hongzhuo Liu, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. IEEE J. Solid State Circuits 60(3): 785-798 (2025) - [j29]Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Lixue Kuang, Lilan Yu, Yue Liu, Xin Liang, Zhihua Wang, Baoyong Chi:
A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC. IEEE J. Solid State Circuits 60(3): 1014-1029 (2025) - [c49]Angxiao Yan, Wei Deng, Haikun Jia, Yumeng Yang, Chao Tang, Shiyan Sun, Zhihua Wang, Baoyong Chi:
19.9 An 11-to-16.4GHz, 3.4GHz/µs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time. ISSCC 2025: 1-3 - 2024
- [j28]Ziyi Lin, Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi:
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer. IEEE J. Solid State Circuits 59(1): 253-267 (2024) - [j27]Fuyuan Zhao, Wei Deng, Haikun Jia, Wenjing Ye, Ruichen Wan, Zhihua Wang, Baoyong Chi:
A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers. IEEE J. Solid State Circuits 59(5): 1323-1336 (2024) - [j26]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Multireference PLL: Theory and Implementation. IEEE J. Solid State Circuits 59(7): 1981-1994 (2024) - [j25]Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. IEEE J. Solid State Circuits 59(8): 2441-2454 (2024) - [j24]Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi:
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits 59(10): 3123-3141 (2024) - [j23]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS. IEEE J. Solid State Circuits 59(10): 3172-3182 (2024) - [j22]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi, Ziqiang Wang:
28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3573-3583 (2024) - [j21]Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
Correction to "A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor-Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer". IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2904 (2024) - [c48]Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Baoyong Chi:
A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression. CICC 2024: 1-2 - [c47]Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi:
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. CICC 2024: 1-2 - [c46]Xinyu Jiang, Wei Deng, Junlong Gong, Haikun Jia, Baoyong Chi:
INVITED PAPER: A 21.5-to-37 GHz Series Doherty CMOS Power Amplifier with Distributed Multi-step Impedance Inverting Network Achieving 28.2%/23.2%/13.2% Peak/OP1dB/6dBPBO PAEs. ICTA 2024: 144-147 - [c45]Junlong Gong, Wei Deng, Fuyuan Zhao, Haikun Jia, Wenjing Ye, Ruichen Wan, Baoyong Chi:
A 24.3-to-44.8 GHz Reconfigurable Dual-Band T/R Front-End with An Implicit Switch-based Antenna Interface Supporting 600MSym/s 64QAM. ISCAS 2024: 1-5 - [c44]Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Zhihua Wang, Baoyong Chi:
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique. ISSCC 2024: 356-358 - [c43]Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi:
A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j20]Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang:
A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS. IET Circuits Devices Syst. 17(3): 174-179 (2023) - [j19]Haikun Jia, Pingda Guan, Wei Deng, Zhihua Wang, Baoyong Chi:
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. IEEE J. Solid State Circuits 58(2): 371-385 (2023) - [j18]Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi:
A D-Band Joint Radar-Communication CMOS Transceiver. IEEE J. Solid State Circuits 58(2): 411-427 (2023) - [j17]Yaqian Sun, Wei Deng, Haikun Jia, Yejun He, Zhihua Wang, Baoyong Chi:
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique. IEEE J. Solid State Circuits 58(10): 2861-2873 (2023) - [j16]Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi:
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1839-1851 (2023) - [c42]Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. A-SSCC 2023: 1-3 - [c41]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO. A-SSCC 2023: 1-3 - [c40]Xiangrong Huang, Haikun Jia, Wei Deng, Chuanming Zhu, Zhihua Wang, Xuzhi Liu, Zhiming Chen, Baoyong Chi:
A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS. A-SSCC 2023: 1-3 - [c39]Dongze Li, Wei Deng, Xintao Li, Ruiheng Qiu, Haikun Jia, Xiangrong Huang, Ziyuan Guo, Baoyong Chi:
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS. A-SSCC 2023: 1-3 - [c38]Ziyi Lin, Haikun Jia, Chuanming Zhu, Wei Deng, Huabing Liao, Bao Shi, Lujie Hao, Xiangrong Huang, Baoyong Chi:
A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver. A-SSCC 2023: 1-3 - [c37]Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi:
IEEE ASSCC 2023/ Session 10/ Paper 10.5. A-SSCC 2023: 1-3 - [c36]Angxiao Yan, Wei Deng, Haikun Jia, Shiwei Zhang, Baoyong Chi:
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation. A-SSCC 2023: 1-3 - [c35]Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, Baoyong Chi:
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS. CICC 2023: 1-2 - [c34]Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi:
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. CICC 2023: 1-2 - [c33]Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Taikun Ma, Jiajie Tang, Baoyong Chi:
Transceiver SoC for Wireless Indoor Sensing Data-fusion. CICC 2023: 1-2 - [c32]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi:
A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. ESSCIRC 2023: 261-264 - [c31]Dongze Li, Wei Deng, Haikun Jia, Ruiheng Qiu, Xintao Li, Ziyuan Guo, Baoyong Chi:
A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers. ESSCIRC 2023: 385-388 - [c30]Shijie Li, Ruichang Ma, Mingxing Deng, Jiamin Xue, Wei Deng, Baoyong Chi, Haikun Jia:
INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS. ICTA 2023: 21-24 - [c29]Ziying Huang, Wei Deng, Haikun Jia, Bufan Zhu, Angxiao Yan, Baoyong Chi:
A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator. ISCAS 2023: 1-4 - [c28]Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. ISSCC 2023: 146-147 - [c27]Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi:
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration. ISSCC 2023: 228-229 - [c26]Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi:
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j15]Wei Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi:
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. IEEE J. Solid State Circuits 57(4): 1162-1174 (2022) - [j14]Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4028-4032 (2022) - [c25]Taikun Ma, Wei Deng, Haikun Jia, Yejun He, Baoyong Chi:
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array. ASP-DAC 2022: 3-4 - [c24]Ruichang Ma, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS. CICC 2022: 1-2 - [c23]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi:
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. ESSCIRC 2022: 233-236 - [c22]Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi:
A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. ICTA 2022: 1-2 - [c21]Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, Wei Deng, Baoyong Chi, Zhihua Wang:
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS. ICTA 2022: 84-85 - [c20]Qixiu Wu, Wei Deng, Haikun Jia, Rui Wu, Fuyuan Zhao, Baoyong Chi:
A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers. ISCAS 2022: 3351-3354 - [c19]Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi:
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS. ISSCC 2022: 154-156 - 2021
- [c18]Wei Deng, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi:
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna. ASP-DAC 2021: 95-96 - [c17]Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS. A-SSCC 2021: 1-3 - [c16]Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi:
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology. A-SSCC 2021: 1-3 - [c15]Wei Deng, Haikun Jia, Rui Wu, Shiyan Sun, Chenggang Li, Zhihua Wang, Baoyong Chi:
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. CICC 2021: 1-2 - [c14]Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique. CICC 2021: 1-2 - [c13]Xiangrong Huang, Wei Deng, Haikun Jia, Yuhui Wei, Zhihua Wang, Baoyong Chi:
A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology. ICTA 2021: 191-192 - [c12]Ziyue Dang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
Optimization methods for high inductance-density inductors for high speed integrated circuits. ICTA 2021: 243-244 - [c11]Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan:
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. ISSCC 2021: 134-136 - [c10]Haikun Jia, Wei Deng, Pingda Guan, Zhihua Wang, Baoyong Chi:
A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS. ISSCC 2021: 298-300 - [c9]Wei Deng, Zipeng Chen, Haikun Jia, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi:
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth. VLSI Circuits 2021: 1-2 - [c8]Zipeng Chen, Wei Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi:
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [j13]Wei Deng, Zheng Song, Ruichang Ma, Jianfu Lin, Yutian Li, Jialiang Ye, Shangcheng Kong, Sanming Hu, Haikun Jia, Baoyong Chi:
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer. IEEE J. Solid State Circuits 55(8): 2027-2042 (2020) - [j12]Zipeng Chen, An'an Li, Haikun Jia, Baoyong Chi:
A 27-31 GHz 6-bit phase shifter with low phase error/gain variation in 65 nm CMOS. Microelectron. J. 104: 104906 (2020) - [j11]Zipeng Chen, Wei Deng, Haikun Jia, Yibo Liu, Jianxi Wu, Pingda Guan, Jinyu Zhu, Luhong Mao, Zhihua Wang, Baoyong Chi:
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1574-1578 (2020) - [j10]Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Haikun Jia, Baoyong Chi:
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2089-2098 (2020) - [c7]Shengnan Dong, Zipeng Chen, Haikun Jia, Wei Deng, Baoyong Chi:
A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process. ICTA 2020: 15-16 - [c6]Chenggang Li, Rui Wu, Haikun Jia, Wei Deng, Baoyong Chi:
A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme. ICTA 2020: 29-30
2010 – 2019
- 2019
- [j9]Haikun Jia, Baoyong Chi:
International Solid-State Circuits Conference 2019 aims at "envisioning the future". Sci. China Inf. Sci. 62(6): 67401:1-67401:2 (2019) - 2018
- [j8]Haikun Jia, Clarissa C. Prawoto, Baoyong Chi, Zhihua Wang, C. Patrick Yue:
A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2657-2668 (2018) - 2017
- [j7]Zhiping Wang, Haikun Jia, Lixue Kuang, Baoyong Chi:
An 80-83 GHz CMOS DCO based on DiCAD technique for size, linearity and noise optimization. Sci. China Inf. Sci. 60(8): 080401:1-080401:3 (2017) - 2016
- [j6]Haikun Jia, Baoyong Chi, Lixue Kuang, Zhihua Wang:
Simple and robust self-healing technique for millimetre-wave amplifiers. IET Circuits Devices Syst. 10(1): 37-43 (2016) - [j5]Haikun Jia, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang, Baoyong Chi:
A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar. IEEE J. Solid State Circuits 51(10): 2299-2311 (2016) - [c5]Haikun Jia, Clarissa C. Prawoto, Baoyong Chi, Zhihua Wang, C. Patrick Yue:
A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators. A-SSCC 2016: 345-348 - 2015
- [j4]Lixue Kuang, Baoyong Chi, Haikun Jia, Wen Jia, Zhihua Wang:
A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 352-356 (2015) - [c4]Baoyong Chi, Lixue Kuang, Haikun Jia, Zhiping Wang, Zhihua Wang:
A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOS. ASICON 2015: 1-4 - [c3]Haikun Jia, Baoyong Chi, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang:
A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. A-SSCC 2015: 1-4 - [c2]Haikun Jia, Baoyong Chi, Zhihua Wang:
An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS. ESSCIRC 2015: 124-127 - [c1]Zhiqiang Huang, Howard Cam Luong, Baoyong Chi, Zhihua Wang, Haikun Jia:
25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter. ISSCC 2015: 1-3 - 2014
- [j3]Haikun Jia, Baoyong Chi, Lixue Kuang, Zhihua Wang:
A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS. Microelectron. J. 45(7): 898-903 (2014) - [j2]Haikun Jia, Baoyong Chi, Lixue Kuang, Zhihua Wang:
A 38- to 40-GHz Current-Reused Active Phase Shifter Based on the Coupled Resonator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 917-921 (2014) - 2012
- [j1]Haikun Jia, Baoyong Chi, Lixue Kuang, Zhihua Wang:
A 1 V, 69-73 GHz CMOS power amplifier based on improved Wilkinson power combiner. Microelectron. J. 43(6): 370-376 (2012)
Coauthor Index
[j31] [j30] [j29] [c49] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [c48] [c47] [c46] [c45] [c44] [c43] [j19] [j18] [j17] [j16] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j15] [j14] [c25] [c24] [c23] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c10] [c9] [c8] [j13] [j12] [j11] [j10] [c7] [c6] [j9] [j8] [j7] [j6] [j5] [c5] [j4] [c4] [c3] [c2] [c1] [j3] [j2] [j1]
[j31] [j30] [j29] [c49] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [c48] [c47] [c46] [c45] [c44] [c43] [j19] [j18] [j17] [j16] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j15] [j14] [c25] [c24] [c23] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c10] [c9] [c8] [j13] [j11] [j10] [c7] [c6]
[j31] [j30] [j29] [c49] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [c44] [c43] [j20] [j19] [j18] [j17] [j16] [c42] [c41] [c40] [c37] [c35] [c28] [c27] [j15] [j14] [c24] [c23] [c21] [c19] [c17] [c16] [c15] [c14] [c13] [c12] [c10] [c9] [c8] [j11] [j8] [j6] [j5] [c5] [j4] [c4] [c3] [c2] [c1] [j3] [j2] [j1]
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last updated on 2025-04-27 18:06 CEST by the dblp team
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