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ORCIDSudhakar Yalamanchili
Sudha Yalamanchili
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- affiliation: Georgia Institute of Technology, Atlanta, USA
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2020 – today
- 2021
[j43]Bahar Asgari
, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili:
Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. IEEE Trans. Computers 70(4): 524-538 (2021)- [j42]Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. J. Signal Process. Syst. 93(6): 659-675 (2021) - [c125]He Xiao, Monodeep Kar, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. ICCAE 2021: 83-88 - 2020
- [c124]Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim:
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. DATE 2020: 157-162 - [c123]Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili:
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. HPCA 2020: 249-260 - [i7]Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler:
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability. CoRR abs/2010.10683 (2020)
2010 – 2019
- 2019
- [j41]Saibal Mukhopadhyay, Yun Long, Burhan Ahmad Mudassar, C. S. Nair, Bartlet H. DeProspo, Hakki Mert Torun, M. Kathaperumal, V. Smet, Duckhwan Kim, Sudhakar Yalamanchili, Madhavan Swaminathan:
Heterogeneous integration for artificial intelligence: Challenges and opportunities. IBM J. Res. Dev. 63(6): 4:1 (2019) - [j40]Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili:
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. IEEE Micro 39(5): 46-54 (2019) - [c122]Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter:
POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. PACT 2019: 481-482 - [c121]Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili:
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. DAC 2019: 233 - 2018
- [j39]Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili:
Instruction-throughput regulation in computer processors with data-center applications. Discret. Event Dyn. Syst. 28(1): 127-158 (2018) - [j38]Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2360-2370 (2018) - [c120]Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler:
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability. ASPLOS 2018: 43-55 - [c119]Yun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A ferroelectric FET based power-efficient architecture for data-intensive computing. ICCAD 2018: 32 - [i6]Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. CoRR abs/1803.06068 (2018) - [i5]Karthik Rao, William J. Song, Yorai Wardi, Sudhakar Yalamanchili:
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks. CoRR abs/1808.09087 (2018) - 2017
- [c118]Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili:
Power regulation in high performance multicore processors. CDC 2017: 2674-2679 - [c117]Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye:
Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. HPCA 2017: 169-180 - [c116]Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim:
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. IISWC 2017: 66-75 - [c115]Chad D. Kersey, Hyesoon Kim, Sudhakar Yalamanchili:
Lightweight SIMT core designs for intelligent 3D stacked DRAM. MEMSYS 2017: 49-59 - [c114]Blaise-Pascal Tine, Sudhakar Yalamanchili:
Pagevault: securing off-chip memory using page-based authentication. MEMSYS 2017: 293-304 - [i4]Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim:
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube. CoRR abs/1706.02725 (2017) - [i3]X. Chen, Yorai Wardi, Sudhakar Yalamanchili:
Power Regulation in High Performance Multicore Processors. CoRR abs/1709.04859 (2017) - [i2]Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training. CoRR abs/1710.04347 (2017) - 2016
- [j37]He Xiao, Wen Yueh, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures. IEEE Comput. Archit. Lett. 15(2): 129-132 (2016) - [j36]Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley:
FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems. ACM Trans. Model. Comput. Simul. 26(2): 11:1-11:26 (2016) - [c113]William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors. HPCA 2016: 594-605 - [c112]Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory. ISCA 2016: 380-392 - [c111]Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili:
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs. ISCA 2016: 583-595 - [c110]Syed Minhaj Hassan, Sudhakar Yalamanchili:
Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems. MEMSYS 2016: 387-394 - [c109]Daniel Zinn, Haicheng Wu, Jin Wang, Molham Aref, Sudhakar Yalamanchili:
General-purpose join algorithms for large graph triangle listing on heterogeneous systems. GPGPU@PPoPP 2016: 12-21 - [c108]Eric Anger, Jeremiah J. Wilke, Sudhakar Yalamanchili:
Power-Constrained Performance Scheduling of Data Parallel Tasks. E2SC@SC 2016: 1-7 - [c107]Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili:
IPA in the loop: Control design for throughput regulation in computer processors. WODES 2016: 141-146 - [i1]Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili:
IPA in the Loop: Control Design for Throughput Regulation in Computer Processors. CoRR abs/1604.02727 (2016) - 2015
- [j35]William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors. IEEE Comput. Archit. Lett. 14(2): 103-106 (2015) - [c106]Karthik Rao, William J. Song, Sudhakar Yalamanchili, Yorai Wardi:
Temperature regulation in multicore processors using adjustable-gain integral controllers. CCA 2015: 810-815 - [c105]X. Chen, H. Xiao, Yorai Wardi, Sudhakar Yalamanchili:
Throughput Regulation in Shared Memory Multicore Processors. HiPC 2015: 12-20 - [c104]Eric Anger, Damian Dechev, Gilbert Hendry, Jeremiah J. Wilke, Sudhakar Yalamanchili:
Application Modeling for Scalable Simulation of Massively Parallel Systems. HPCC/CSS/ICESS 2015: 238-247 - [c103]William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Managing performance-reliability tradeoffs in multicore processors. IRPS 2015: 3 - [c102]Indrani Paul, Wei Huang, Manish Arora, Sudhakar Yalamanchili:
Harmonia: balancing compute and memory power in high-performance GPUs. ISCA 2015: 54-65 - [c101]Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili:
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs. ISCA 2015: 528-540 - [c100]Syed Minhaj Hassan, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore. MEMSYS 2015: 11-21 - [c99]Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim:
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. MEMSYS 2015: 29-30 - [c98]Hyojong Kim, Hyesoon Kim, Sudhakar Yalamanchili, Arun F. Rodrigues:
Understanding Energy Aspects of Processing-near-Memory for HPC Workloads. MEMSYS 2015: 276-282 - [e5]Kirk W. Cameron, Adolfy Hoisie, Darren J. Kerbyson, David K. Lowenthal, Dimitrios S. Nikolopoulos, Sudha Yalamanchili, Laura Carrington, Joseph B. Manzano:
Proceedings of the 3rd International Workshop on Energy Efficient Supercomputing, E2SC 2015, Austin, Texas, USA, November 15, 2015. ACM 2015, ISBN 978-1-4503-3994-0 [contents] - 2014
- [j34]Zhimin Wan, He Xiao, Yogendra Joshi, Sudhakar Yalamanchili:
Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. Microelectron. J. 45(12): 1814-1821 (2014) - [j33]Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili:
Coordinated energy management in heterogeneous processors. Sci. Program. 22(2): 93-108 (2014) - [j32]Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William J. Song, Sudhakar Yalamanchili, Wonyong Sung:
Power Modeling for GPU Architectures Using McPAT. ACM Trans. Design Autom. Electr. Syst. 19(3): 26:1-26:24 (2014) - [j31]Borislav Alexandrov, Owen Sullivan, William J. Song, Sudhakar Yalamanchili, Satish Kumar, Saibal Mukhopadhyay:
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1909-1919 (2014) - [c97]Naila Farooqui, Karsten Schwan, Sudhakar Yalamanchili:
Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution. GPGPU@ASPLOS 2014: 19 - [c96]Jin Wang, Norman Rubin, Sudhakar Yalamanchili:
ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems. GPGPU@ASPLOS 2014: 72 - [c95]Haicheng Wu, Gregory F. Diamos, Tim Sheard, Molham Aref, Sean Baxter, Michael Garland, Sudhakar Yalamanchili:
Red Fox: An Execution Environment for Relational Query Processing on GPUs. CGO 2014: 44 - [c94]Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim:
Harmonica: An FPGA-Based Data Parallel Soft Core. FCCM 2014: 171 - [c93]Jin Wang, Sudhakar Yalamanchili:
Characterization and analysis of dynamic parallelism in unstructured GPU applications. IISWC 2014: 51-60 - [c92]Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili:
Manifold: A parallel simulation framework for multicore systems. ISPASS 2014: 106-115 - [c91]William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures. ISPASS 2014: 143-144 - [c90]Syed Minhaj Hassan, Sudhakar Yalamanchili:
Bubble sharing: Area and energy efficient adaptive routers using centralized buffers. NOCS 2014: 119-126 - [c89]Eric Anger, Sudhakar Yalamanchili, Scott Pakin, Patrick S. McCormick:
Architecture-independent modeling of intra-node data movement. LLVM@SC 2014: 29-39 - [c88]Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili:
An efficient front-end for timing-directed parallel simulation of multi-core system. SimuTools 2014: 201-206 - [c87]Haicheng Wu, Daniel Zinn, Molham Aref, Sudhakar Yalamanchili:
Multipredicate Join Algorithms for Accelerating Relational Graph Processing on GPUs. ADMS@VLDB 2014: 1-12 - [e4]Davide Bertozzi, Luca Benini, Sudhakar Yalamanchili, Jörg Henkel:
Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014. IEEE 2014, ISBN 978-1-4799-5347-9 [contents] - [e3]Kirk W. Cameron, Adolfy Hoisie, Darren J. Kerbyson, David K. Lowenthal, Dimitrios S. Nikolopoulos, Sudha Yalamanchili, Andres Marquez:
Proceedings of the 2nd International Workshop on Energy Efficient Supercomputing, E2SC '14, New Orleans, Louisiana, USA, November 16-21, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-7036-0 [contents] - 2013
- [j30]Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili:
Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture. J. Parallel Distributed Comput. 73(12): 1525-1538 (2013) - [j29]Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili:
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures. ACM Trans. Design Autom. Electr. Syst. 18(4): 48:1-48:28 (2013) - [c86]Jin Wang, Norman Rubin, Haicheng Wu, Sudhakar Yalamanchili:
Accelerating simulation of agent-based models on heterogeneous architectures. GPGPU@ASPLOS 2013: 108-119 - [c85]Jeffrey S. Young, Se Hoon Shon, Sudhakar Yalamanchili, Alex Merritt, Karsten Schwan, Holger Fröning:
Oncilla: A GAS runtime for efficient resource allocation and data movement in accelerated clusters. CLUSTER 2013: 1-8 - [c84]Indrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili:
Cooperative boosting: needy versus greedy power management. ISCA 2013: 285-296 - [c83]Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili:
A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems. MASCOTS 2013: 375-379 - [c82]Syed Minhaj Hassan, Sudhakar Yalamanchili:
Centralized buffer router: A low latency, low power router for high radix NOCs. NOCS 2013: 1-8 - [c81]Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley:
Optimizing parallel simulation of multicore systems using domain-specific knowledge. SIGSIM-PADS 2013: 127-136 - [c80]Gregory Frederick Diamos, Haicheng Wu, Jin Wang, Ashwin Sanjay Lele, Sudhakar Yalamanchili:
Relational algorithms for multi-bulk-synchronous processors. PPoPP 2013: 301-302 - [c79]Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili:
Coordinated energy management in heterogeneous processors. SC 2013: 59:1-59:12 - [e2]Kirk W. Cameron, Darren J. Kerbyson, Andres Marquez, Dimitrios S. Nikolopoulos, Sudha Yalamanchili, Kevin J. Barker:
Proceedings of the 1st International Workshop on Energy Efficient Supercomputing, E2SC 2013, Denver, Colorado, USA, November 17-21, 2013. ACM 2013, ISBN 978-1-4503-2504-2 [contents] - 2012
- [j28]Haicheng Wu, Gregory F. Diamos, Jin Wang, Si Li, Sudhakar Yalamanchili:
Characterization and transformation of unstructured control flow in bulk synchronous GPU applications. Int. J. High Perform. Comput. Appl. 26(2): 170-185 (2012) - [c78]Nawaf I. Almoosa, William J. Song, Yorai Wardi, Sudhakar Yalamanchili:
A power capping controller for multicore processors. ACC 2012: 4709-4714 - [c77]Nawaf I. Almoosa, William J. Song, Sudhakar Yalamanchili, Yorai Wardi:
Throughput regulation in multicore processors via IPA. CDC 2012: 7267-7272 - [c76]Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili:
Dynamic compilation of data-parallel kernels for vector processors. CGO 2012: 23-32 - [c75]Andrew Kerr, Eric Anger, Gilbert Hendry, Sudhakar Yalamanchili:
Eiger: A framework for the automated synthesis of statistical performance models. HiPC 2012: 1-6 - [c74]Jeffrey S. Young, Sudhakar Yalamanchili:
Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds. HPCC-ICESS 2012: 303-310 - [c73]Indrani Paul, Sudhakar Yalamanchili, Lizy K. John:
Performance impact of virtual machine placement in a datacenter. IPCCC 2012: 424-431 - [c72]Haicheng Wu, Gregory F. Diamos, Jin Wang, Srihari Cadambi, Sudhakar Yalamanchili, Srimat T. Chakradhar:
Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission. IPDPS Workshops 2012: 2433-2442 - [c71]Naila Farooqui, Andrew Kerr, Greg Eisenhauer, Karsten Schwan, Sudhakar Yalamanchili:
Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures. ISPASS 2012: 58-67 - [c70]Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili:
Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. MICRO 2012: 107-118 - [c69]Chad D. Kersey, Arun Rodrigues, Sudhakar Yalamanchili:
A universal parallel front-end for execution driven microarchitecture simulation. RAPIDO 2012: 25-32 - [c68]Jun Wang, Jesse G. Beu, Sudhakar Yalamanchili, Tom Conte:
Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. SC Companion 2012: 472-476 - [c67]Jeffrey S. Young, Haicheng Wu, Sudhakar Yalamanchili:
Satisfying Data-Intensive Queries Using GPU Clusters. SC Companion 2012: 1314 - [c66]William J. Song, Sudhakar Yalamanchili, Arun F. Rodrigues, Saibal Mukhopadhyay:
Instruction-based energy estimation methodology for asymmetric manycore processor simulations. SimuTools 2012: 166-171 - 2011
- [j27]Jeffrey S. Vetter, Richard Glassbrook, Jack J. Dongarra, Karsten Schwan, Bruce Loftis, Stephen Taylor McNally, Jeremy S. Meredith, James H. Rogers, Philip C. Roth, Kyle Spafford, Sudhakar Yalamanchili:
Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community. Comput. Sci. Eng. 13(5): 90-95 (2011) - [j26]Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 809-817 (2011) - [c65]Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili:
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. PACT 2011: 187-188 - [c64]Naila Farooqui, Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili, Karsten Schwan:
A framework for dynamically instrumenting GPU compute applications within GPU Ocelot. GPGPU 2011: 9 - [c63]Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili:
SIMD re-convergence at thread frontiers. MICRO 2011: 477-488 - [r2]Sudhakar Yalamanchili:
Interconnection Networks. Encyclopedia of Parallel Computing 2011: 964-975 - [r1]Sudhakar Yalamanchili:
Switching Techniques. Encyclopedia of Parallel Computing 2011: 1977-1989 - 2010
- [c62]Gregory Frederick Diamos, Andrew Kerr, Sudhakar Yalamanchili, Nathan Clark:
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. PACT 2010: 353-364 - [c61]Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili:
HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. ARCS 2010: 1 - [c60]Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili:
Modeling GPU-CPU workloads and systems. GPGPU 2010: 31-42 - [c59]Jeffrey S. Young, Sudhakar Yalamanchili:
Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization. Green Computing Conference 2010: 485-492 - [c58]Nawaf I. Almoosa, Yorai Wardi, Sudhakar Yalamanchili:
Controller design for tracking induced miss-rates in cache memories. ICCA 2010: 1355-1359 - [c57]Gregory F. Diamos, Sudhakar Yalamanchili:
Speculative execution on multi-GPU systems. IPDPS 2010: 1-12 - [c56]Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED 2010: 389-394
2000 – 2009
- 2009
- [c55]Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD 2009: 474-477 - [c54]Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili:
A characterization and analysis of PTX kernels. IISWC 2009: 3-12 - [c53]Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee:
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. ISVLSI 2009: 25-30 - 2008
- [c52]Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan:
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. FCCM 2008: 265-268 - [c51]Subramanian Ramaswamy, Sudhakar Yalamanchili:
An Utilization Driven Framework for Energy Efficient Caches. HiPC 2008: 583-594 - [c50]Gregory F. Diamos, Sudhakar Yalamanchili:
Harmony: an execution model and runtime for heterogeneous many core systems. HPDC 2008: 197-200 - 2007
- [c49]Subramanian Ramaswamy, Sudhakar Yalamanchili:
Customized Placement for High Performance Embedded Processor Caches. ARCS 2007: 69-82 - [c48]Subramanian Ramaswamy, Sudhakar Yalamanchili:
Improving cache efficiency via resizing + remapping. ICCD 2007: 47-54 - 2006
- [j25]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
MMR: A MultiMedia Router architecture to support hybrid workloads. J. Parallel Distributed Comput. 66(2): 307-321 (2006) - [j24]Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, Krishna V. Palem:
Data trace cache: an application specific cache architecture. SIGARCH Comput. Archit. News 34(1): 11-18 (2006) - [c47]Subramanian Ramaswamy, Sudhakar Yalamanchili:
Customizable Fault Tolerant Caches for Embedded Processors. ICCD 2006: 108-113 - 2005
- [j23]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router. IEEE Trans. Parallel Distributed Syst. 16(11): 1009-1021 (2005) - 2004
- [c46]Krishna V. Palem, Lakshmi N. Chakrapani, Sudhakar Yalamanchili:
A Framework for Compiler Driven Design Space Exploration for Embedded System Customization. ASIAN 2004: 395-406 - [c45]Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West:
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. FCCM 2004: 115-124 - 2003
- [c44]Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West:
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture. IPDPS 2003: 30 - [c43]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR. IPDPS 2003: 197 - [c42]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR. PDPTA 2003: 220-226 - 2002
- [c41]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
A new switch scheduling algorithm to improve QoS in the multimedia router. IEEE Workshop on Multimedia Signal Processing 2002: 376-379 - [c40]Indrani Paul, Sudhakar Yalamanchili, José Duato:
Algorithms for Switch-Scheduling in the Multimedia Router for LANs. HiPC 2002: 219-231 - [c39]Sudhakar Yalamanchili:
The Customization Landscape for Embedded Systems. HiPC 2002: 693-696 - [c38]Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West:
Architecture and Hardware for Scheduling Gigabit Packet Streams. Hot Interconnects 2002: 52-64 - [c37]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
A multimedia router architecture to provide high performance and QoS guarantees to mixed traffic. ICME (1) 2002: 313-316 - [c36]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router. IPDPS 2002 - [c35]Craig D. Ulmer, Sudhakar Yalamanchili:
A Tunable Communications Library for Data Injection. PDPTA 2002: 1630-1636 - 2001
- [c34]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR). ICN (2) 2001: 358-369 - [c33]María Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili:
Tuning Buffer Size in the Multimedia Router (MMR). IPDPS 2001: 160 - 2000
- [j22]Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili:
Software-Based Rerouting for Fault-Tolerant Pipelined Communication. IEEE Trans. Parallel Distributed Syst. 11(3): 193-211 (2000) - [j21]Young-Joo Suh, Sudhakar Yalamanchili:
Configurable Algorithms for Complete Exchange in 2D Meshes. IEEE Trans. Parallel Distributed Syst. 11(4): 337-356 (2000) - [c32]Damon S. Love, Sudhakar Yalamanchili, José Duato, María Blanca Caminero, Francisco J. Quiles:
Switch Scheduling in the Multimedia Router (MMR). IPDPS 2000: 5-12 - [c31]Craig D. Ulmer, Sudhakar Yalamanchili:
An Extensible Message Layer for High-Performance Clusters. PDPTA 2000
1990 – 1999
- 1999
- [j20]Binh Vien Dao, José Duato, Sudhakar Yalamanchili:
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing. IEEE Trans. Parallel Distributed Syst. 10(1): 7-22 (1999) - [c30]María Blanca Caminero, Francisco J. Quiles, José Duato, Damon S. Love, Sudhakar Yalamanchili:
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic. CANPC 1999: 62-76 - [c29]Richard West, Raj Krishnamurthy, W. K. Norton, Karsten Schwan, Sudhakar Yalamanchili, Marcel-Catalin Rosu, V. Sarat:
QUIC: A Quality of Service Network Interface Layer for Communication in NOWs. Heterogeneous Computing Workshop 1999: 199-208 - [c28]José Duato, Sudhakar Yalamanchili, María Blanca Caminero, Damon S. Love, Francisco J. Quiles:
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. HPCA 1999: 300-309 - [c27]Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford:
Teaching Pipelining and Concurrency using Hardware Description Languages. MSE 1999: 55-56 - 1998
- [j19]Young-Joo Suh, Sudhakar Yalamanchili:
All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes. IEEE Trans. Parallel Distributed Syst. 9(5): 442-458 (1998) - [c26]Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili:
FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems. IEEE Real Time Technology and Applications Symposium 1998: 79-84 - [e1]Sudhakar Yalamanchili, José Duato:
Parallel Computer Routing and Communication, Second International Workshop, PCRCW'97, Atlanta, Georgia, USA, June 26-27, 1997, Proceedings. Lecture Notes in Computer Science 1417, Springer 1998, ISBN 3-540-64571-3 [contents] - 1997
- [b1]José Duato, Sudhakar Yalamanchili, Lionel M. Ni:
Interconnection networks - an engineering approach. IEEE 1997, ISBN 978-0-8186-7800-4, pp. I-XVIII, 1-515 - [c25]Binh Vien Dao, Sudhakar Yalamanchili, José Duato:
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks. HPCA 1997: 343-352 - [c24]Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel:
Power Constrained Design of Multiprocessor Interconnection Networks. ICCD 1997: 408-416 - [c23]José Duato, Pedro López, Sudhakar Yalamanchili:
Deadlock- and Livelock-Free Routing Protocols for Wave Switching. IPPS 1997: 570-577 - [c22]Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel:
Power/Performance Trade-offs for Direct Networks. PCRCW 1997: 231-246 - [c21]Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili, Rakesh Jha:
On adaptive resource allocation for complex real-time application. RTSS 1997: 320-329 - 1996
- [j18]Sudhakar Yalamanchili, Todd Carpenter:
Paradigms for Modeling and Simulation of Multiprocessor Architectures. Int. J. Comput. Simul. 6(1): 137- (1996) - [j17]Patrick T. Gaughan, Binh Vien Dao, Sudhakar Yalamanchili, David E. Schimmel:
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks. IEEE Trans. Computers 45(6): 651-665 (1996) - [j16]Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili:
Augmented Binary Hypercube: A New Architecture for Processor Management. IEEE Trans. Computers 45(8): 980-984 (1996) - [c20]Vivek Garg, Steve Lacy, David E. Schimmel, Darrell Stogner, Craig D. Ulmer, D. Scott Wills, Sudhakar Yalamanchili:
Incorporating Multi-Chip Module Packaging Constraints into System Design. ED&TC 1996: 508-513 - [c19]Rakesh Jha, Mustafa Muhammad, Sudhakar Yalamanchili, Karsten Schwan, Daniela Ivan-Rosu, Chris deCastro:
Adaptive resource allocation for embedded parallel applications. HiPC 1996: 425-431 - [c18]José Duato, Pedro López, Federico Silla, Sudhakar Yalamanchili:
A High Performance Router Architecture for Interconnection Networks. ICPP, Vol. 1 1996: 61-68 - [c17]Young-Joo Suh, Sudhakar Yalamanchili:
Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori. IPPS 1996: 808-814 - [c16]Emily Angerer Crawford, Karsten Schwan, Sudhakar Yalamanchili:
Optimistic parallel computation: an example from computational chemistry. SPDP 1996: 214-217 - [c15]James O. Hamblen, Henry Owen, Sudhakar Yalamanchili, Binh Vien Dao:
Using rapid prototyping in computer architecture design laboratories. WCAE@HPCA 1996: 4 - 1995
- [j15]Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy:
Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints. Concurr. Pract. Exp. 7(3): 167-189 (1995) - [j14]Patrick T. Gaughan, Sudhakar Yalamanchili:
A Performance Model of Pipelined K-ary n-cubes. IEEE Trans. Computers 44(8): 1059-1063 (1995) - [j13]Hatem Sellami, Sudhakar Yalamanchili:
Parallelism in Sequential Multiprocessor Simulation Models: A Case Study. ACM Trans. Model. Comput. Simul. 5(2): 101-128 (1995) - [j12]Patrick T. Gaughan, Sudhakar Yalamanchili:
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks. IEEE Trans. Parallel Distributed Syst. 6(5): 482-497 (1995) - [c14]Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili:
Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks. ICPP (1) 1995: 101-105 - [c13]Hatem Sellami, Sudhakar Yalamanchili:
Time scale combining of conservative parallel discrete event simulations. IPPS 1995: 599-603 - [c12]Binh Vien Dao, José Duato, Sudhakar Yalamanchili:
Configurable Flow Control Mechanisms for Fault-Tolerant Routing. ISCA 1995: 220-229 - 1994
- [j11]Christopher H. de Castro, Sudhakar Yalamanchili:
Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures. Int. J. Comput. Simul. 4(4): 395-417 (1994) - [j10]Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili:
Large Join Optimization on a Hypercube Multiprocessor. IEEE Trans. Knowl. Data Eng. 6(2): 304-315 (1994) - [c11]José Duato, V. B. Dao, Patrick T. Gaughan, Sudhakar Yalamanchili:
Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks. ICPADS 1994: 608-613 - [c10]James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili:
Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. ISCA 1994: 278-288 - [c9]Hatem Sellami, James D. Allen, David E. Schimmel, Sudhakar Yalamanchili:
Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management. MASCOTS 1994: 343-348 - 1993
- [j9]Patrick T. Gaughan, Sudhakar Yalamanchili:
Adaptive Routing Protocols for Hypercube Interconnection Networks. Computer 26(5): 12-23 (1993) - [c8]Patrick T. Gaughan, Sudhakar Yalamanchili:
Analytical Models of Bandwidth Allocation in Pipelined k-ary n-cubes. IPPS 1993: 395-400 - [c7]Hatem Sellami, Sudhakar Yalamanchili:
Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models. SPDP 1993: 360-367 - [c6]Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy:
Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors. SPDP 1993: 522-529 - 1992
- [c5]Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili:
Parallel Optimization and Execution of Large Join Queries. FGCS 1992: 907-914 - [c4]Ajay Mohindra, Sudhakar Yalamanchili:
Dominant Representations: A Paradigm for Mapping Parallel Computations. IPPS 1992: 67-71 - [c3]Patrick T. Gaughan, Sudhakar Yalamanchili:
Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing. SPDP 1992: 148-155 - 1991
- [c2]Steven D. Young, Sudhakar Yalamanchili:
Adaptive routing in generalized hypercube architectures. SPDP 1991: 564-571
1980 – 1989
- 1987
- [j8]S. Y. Lee, Sudhakar Yalamanchili, Jake K. Aggarwal:
Parallel image normalization on a mesh connected array processor. Pattern Recognit. 20(1): 115-124 (1987) - [j7]Sudhakar Yalamanchili, Jake K. Aggarwal:
A Characterization and Analysis of Parallel Processor Interconnection Networks. IEEE Trans. Computers 36(6): 680-691 (1987) - 1985
- [j6]Sudhakar Yalamanchili, Jake K. Aggarwal:
Reconfiguration Strategies for Parallel Architectures. Computer 18(12): 44-61 (1985) - [j5]Sudhakar Yalamanchili, Jake K. Aggarwal:
Analysis of a model for parallel image processing. Pattern Recognit. 18(1): 1-16 (1985) - [j4]Sudhakar Yalamanchili, Jake K. Aggarwal:
A system organization for parallel image processing. Pattern Recognit. 18(1): 17-29 (1985) - 1984
- [j3]Sudhakar Yalamanchili, Miroslaw Malek, Jake K. Aggarwal:
Workstations in a Local Area Network Environment. Computer 17(11): 74-86 (1984) - [j2]Sudhakar Yalamanchili, Jake K. Aggarwal:
Formulation of parallel image processing tasks. Pattern Recognit. Lett. 2(4): 261-270 (1984) - [c1]Sudhakar Yalamanchili, Jake K. Aggarwal:
Algebraic Properties of some Parallel Processor Interconnection Networks. ICDE 1984: 611-618 - 1982
- [j1]Sudhakar Yalamanchili, Worthy N. Martin, Jake K. Aggarwal:
Extraction of moving object descriptions via differencing. Comput. Graph. Image Process. 18(2): 188-201 (1982)
Coauthor Index
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