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2010 – 2019
- 2019
[j64]Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada:
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16(19): 20190390 (2019)- [j63]Daigo Takahashi
, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68(7): 2519-2530 (2019) - [j62]Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 11-19 (2019) - 2018
- [j61]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - [j60]Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda:
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15(5) (2018) - [j59]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 410-424 (2018) - [j58]Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada:
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. 101-C(4): 218-223 (2018) - [j57]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. 101-C(4): 292-298 (2018) - [j56]Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada:
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67(4): 745-753 (2018) - [c127]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS 2018: 408-411 - [c126]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) 2018: 1-13 - [c125]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC 2018: 55-58 - 2017
- [j55]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 200-209 (2017) - [j54]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. 100-C(9): 736-745 (2017) - [j53]Nguyen Ngoc Mai Khanh, Kunihiro Asada:
A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications. IEICE Trans. Electron. 100-C(12): 1078-1086 (2017) - [j52]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2741-2749 (2017) - [c124]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC 2017: 23-24 - [c123]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. ASP-DAC 2017: 29-30 - [c122]Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging 2017: 18-23 - [c121]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS 2017: 1-2 - [c120]Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS 2017: 1-4 - [c119]Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS 2017: 231-234 - [c118]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS 2017: 318-321 - [c117]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS 2017: 257-260 - 2016
- [j51]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32(3): 257-271 (2016) - [j50]Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada:
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. 99-C(2): 275-284 (2016) - [j49]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. 99-C(10): 1219-1225 (2016) - [j48]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25(3): 1640017:1-1640017:16 (2016) - [c116]Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC 2016: 313-316 - [c115]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE 2016: 517-522 - [c114]Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC 2016: 301-304 - [c113]Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada:
One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME 2016: 1-3 - [c112]Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS 2016: 29-32 - [c111]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Resonant power supply noise reduction using a triangular active charge injection. ICECS 2016: 113-116 - [c110]Masahiro Kano, Toru Nakura, Kunihiro Asada:
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED 2016: 386-391 - [c109]Toru Nakura, Kunihiro Asada:
Fully automated PLL compiler generating final GDS from specification. ISQED 2016: 437-442 - [c108]Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC 2016: 1-8 - [c107]James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada:
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS 2016: 1-4 - 2015
- [j47]Toru Nakura, Hiroaki Matsui, Kunihiro Asada:
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express 12(3): 20141114 (2015) - [j46]Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada:
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. 98-C(7): 734-740 (2015) - [j45]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64(4): 840-848 (2015) - [c106]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC 2015: 1-4 - [c105]Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada:
A Technique for Analyzing On-Chip Power Supply Impedance. ATS 2015: 193-198 - [c104]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS 2015: 131-136 - [c103]Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS 2015: 1-4 - 2014
- [j44]Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada:
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 777-780 (2014) - [j43]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1688-1698 (2014) - [c102]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS 2014: 168-173 - [c101]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Burst-pulse Generator based on transmission line toward sub-MMW. DDECS 2014: 59-64 - [c100]Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada:
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS 2014: 282-285 - [c99]Toru Nakura, Kunihiro Asada:
Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME 2014: 133-136 - [c98]Hongbo Zhu, Kunihiro Asada:
A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique. ICECS 2014: 363-366 - [c97]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS 2014: 93-96 - [c96]Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada:
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC 2014: 1-10 - [c95]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS 2014: 111-114 - 2013
- [j42]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. 96-C(4): 518-527 (2013) - [j41]Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. 96-C(4): 560-567 (2013) - [j40]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2458-2466 (2013) - [c94]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260 - [c93]Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada:
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC 2013: 1-4 - [c92]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4 - [c91]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC 2013: 1-4 - [c90]Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Pulse Width controlled PLL and its automated design flow. ICECS 2013: 5-8 - [c89]Tomohiko Yano, Toru Nakura, Kunihiro Asada:
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS 2013: 625-628 - [c88]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76 - [c87]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC 2013: 1-8 - 2012
- [j39]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS. IEICE Electron. Express 9(12): 1057-1061 (2012) - [j38]Toru Nakura, Kunihiro Asada:
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. 95-C(2): 297-302 (2012) - [j37]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. 95-C(4): 546-554 (2012) - [j36]Tetsuya Iizuka, Kunihiro Asada:
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. 95-C(4): 627-634 (2012) - [j35]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. 95-C(4): 643-650 (2012) - [j34]Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada:
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. 95-C(4): 661-667 (2012) - [j33]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. 95-C(12): 1857-1863 (2012) - [j32]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2234-2241 (2012) - [c86]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC 2012: 150-157 - [c85]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira:
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190 - [c84]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257 - [c83]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4 - [c82]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips 2012: 1-3 - [c81]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
Range extension of inductive coupling communication using multi-stage resonance. ISCIT 2012: 758-763 - [c80]James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED 2012: 27-32 - [c79]Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC 2012: 1-10 - 2011
- [j31]Tetsuya Iizuka, Kunihiro Asada:
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8(1): 20-25 (2011) - [j30]Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada:
Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Trans. Electron. 94-C(1): 124-127 (2011) - [j29]Salih Ergün, Ülkühan Güler, Kunihiro Asada:
A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 180-190 (2011) - [j28]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. 94-C(4): 487-494 (2011) - [j27]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. 94-C(4): 511-519 (2011) - [j26]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability. IEICE Trans. Electron. 94-C(4): 627-634 (2011) - [j25]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. 94-C(4): 654-662 (2011) - [j24]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. 94-C(6): 1098-1104 (2011) - [j23]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging. IEICE Trans. Electron. 94-C(10): 1626-1633 (2011) - [j22]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2554-2562 (2011) - [j21]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits 46(11): 2500-2513 (2011) - [c78]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76 - [c77]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 - [c76]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. ASP-DAC 2011: 107-108 - [c75]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114 - [c74]Tetsuya Iizuka, Kunihiro Asada:
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120 - [c73]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186 - [c72]Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada:
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402 - [c71]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS 2011: 53-56 - [c70]Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS 2011: 220-223 - [c69]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610 - [c68]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532 - [c67]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED 2011: 3-8 - [c66]Teruki Nakasato, Toru Nakura, Kunihiro Asada:
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC 2011: 150-153 - [c65]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10 - 2010
- [j20]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express 7(13): 943-948 (2010) - [j19]Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. 93-C(3): 303-308 (2010) - [j18]Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1319-1328 (2010) - [c64]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356 - [c63]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE 2010: 1755-1760 - [c62]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172 - [c61]Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe:
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. DFT 2010: 3 - [c60]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC 2010: 182-185 - [c59]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC 2010: 266-269 - [c58]Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. ISSCC 2010: 404-405
2000 – 2009
- 2009
- [j17]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. 92-C(6): 798-805 (2009) - [c57]Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada:
Circuit design using stripe-shaped PMELA TFTs on glass. ASP-DAC 2009: 105-106 - [c56]Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda:
Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131 - [c55]Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209 - [c54]Toru Nakura, Yutaro Tatemura, Görschwin Fey