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Yu-Liang Wu

David Yu-Liang Wu

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affiliation: Chinese University of Hong Kong

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Journal Articles

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2022
[j23]
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Jung-Chao Ban, Chih-Hung Chang, Wen-Guei Hu, Yu-Liang Wu:
Topological entropy for shifts of finite type over Z and trees. Theor. Comput. Sci. 930: 24-32 (2022)
2018
[j22]
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Bing-Fei Wu, Po-Wei Huang, Chun-Hsien Lin, Meng-Liang Chung, Tsong-Yang Tsou, Yu-Liang Wu:
Motion Resistant Image-Photoplethysmography Based on Spectral Peak Tracking Algorithm. IEEE Access 6: 21621-21634 (2018)
2013
[j21]
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Hongbing Fan, Yu-Liang Wu, Ray C. C. Cheung:
Design Automation Framework for Reconfigurable Interconnection Networks. Comput. J. 56(2): 258-269 (2013)
[j20]
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Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone:
Testing of Synchronizers in Asynchronous FIFO. J. Electron. Test. 29(1): 49-72 (2013)
2012
[j19]
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Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu:
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. ACM Trans. Design Autom. Electr. Syst. 17(4): 50:1-50:21 (2012)
2011
[j18]
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Fu-Shing Chim, Tak-Kei Lam, Yu-Liang Wu, Hongbing Fan:
On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2853-2865 (2011)
2008
[j17]
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Jian-Liang Wu, Yu-Liang Wu:
The Vertex Linear Arboricity of Claw-Free Graphs with Small Degree. Ars Comb. 86 (2008)
2007
[j16]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
The exact channel density and compound design for generic universal switch blocks. ACM Trans. Design Autom. Electr. Syst. 12(2): 19 (2007)
2006
[j15]
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Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu:
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. IEEE Trans. Computers 55(4): 373-384 (2006)
2005
[j14]
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
A dual-mode built-in self-test technique for capacitive MEMS devices. IEEE Trans. Instrum. Meas. 54(5): 1739-1750 (2005)
2003
[j13]
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Jiping Liu, Hongbing Fan, Dinah de Porto, Yu-Liang Wu:
An Efficient Exact Router for Hyper-Universal Switching Box. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(6): 1430-1436 (2003)
[j12]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu:
General Models and a Reduction Design Technique for FPGA Switch Box Designs. IEEE Trans. Computers 52(1): 21-30 (2003)
[j11]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On optimal hyperuniversal and rearrangeable switch box designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1637-1649 (2003)
[j10]
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Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan:
Further improve circuit partitioning using GBAW logic perturbation techniques. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 451-460 (2003)
2002
[j9]
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Yu-Liang Wu, Wenqi Huang, Siu-Chung Lau, C. K. Wong, Gilbert H. Young:
An effective quasi-human based heuristic for solving the rectangle packing problem. Eur. J. Oper. Res. 141(2): 341-358 (2002)
[j8]
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Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian:
Accelerating Logic Rewiring Using Implication Analysis Tree. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2725-2736 (2002)
[j7]
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Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang:
Comment on Generic Universal Switch Blocks. IEEE Trans. Computers 51(1): 93-96 (2002)
[j6]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong:
Reduction design for generic universal switch blocks. ACM Trans. Design Autom. Electr. Syst. 7(4): 526-546 (2002)
2001
[j5]
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Hongbing Fan, Yu-Liang Wu, C. K. Wong:
On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks. Graphs Comb. 17(2): 213-225 (2001)
2000
[j4]
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Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong:
OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers 49(12): 1371-1379 (2000)
1998
[j3]
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  - journals/integration/PanWWY98
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Jiaofeng Pan, Yu-Liang Wu, C. K. Wong, Guiying Yan:
On the optimal four-way switch box routing structures of FPGA greedy routing architectures1. Integr. 25(2): 137-159 (1998)
1997
[j2]
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Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing for array-type FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 506-518 (1997)
1996
[j1]
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  - journals/tcad/WuTM96
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Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
Graph based analysis of 2-D FPGA routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 33-44 (1996)

Conference and Workshop Papers

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2023
[c62]
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  - conf/cvpr/LiZTGYLLJWHLJLFLWCLZFSMZWZSPDTYWPCDZKV23
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Yawei Li, Yulun Zhang, Radu Timofte, Luc Van Gool, Lei Yu, Youwei Li, Xinpeng Li, Ting Jiang, Qi Wu, Mingyan Han, Wenjie Lin, Chengzhi Jiang, Jinting Luo, Haoqiang Fan, Shuaicheng Liu, Yucong Wang, Minjie Cai, Mingxi Li, Yuhang Zhang, Xianjun Fan, Yankai Sheng, Yanyu Mao, Nihao Zhang, Qian Wang, Mingjun Zheng, Long Sun, Jinshan Pan, Jiangxin Dong, Jinhui Tang, Zhongbao Yang, Yan Wang, Erlin Pan, Qixuan Cai, Xinan Dai, Magauiya Zhussip, Nikolay Kalyazin, Dmitry Vyal, Xueyi Zou, Youliang Yan, Heaseo Chung, Jin Zhang, Gaocheng Yu, Feng Zhang, Hongbin Wang, Bohao Liao, Zhibo Du, Yu-Liang Wu, Gege Shi, Long Peng, Yang Wang, Yang Cao, Zhengjun Zha, Zhi-Kai Huang, Yi-Chung Chen, Yuan-Chun Chiang, Hao-Hsiang Yang, Wei-Ting Chen, Hua-En Chang, I-Hsiang Chen, Chia-Hsuan Hsieh, Sy-Yen Kuo, Xin Liu, Jiahao Pan, Hongyuan Yu, Weichen Yu, Lin Ge, Jiahua Dong, Yajun Zou, Zhuoyuan Wu, Binnan Han, Xiaolin Zhang, Heng Zhang, Xuanwu Yin, Kunlong Zuo, Weijian Deng, Hongjie Yuan, Zengtong Lu, Mingyu Ouyang, Wenzhuo Ma, Nian Liu, Hanyou Zheng, Yuantong Zhang, Junxi Zhang, Zhenzhong Chen, Garas Gendy, Nabil Sabor, Jingchao Hou, Guanghui He, Yurui Zhu, Xi Wang, Xueyang Fu, Zheng-Jun Zha, Daheng Yin, Mengyang Liu, Baijun Chen, Ao Li, Lei Luo, Kangjun Jin, Ce Zhu, Xiaoming Zhang, Chengxing Xie, Linze Li, Haiteng Meng, Tianlin Zhang, Tianrui Li, Xiaole Zhao, Zhao Zhang, Baiang Li, Huan Zheng, Suiyi Zhao, Yangcheng Gao, Jiahuan Ren, Kang Hu, Jingpeng Shi, Zhijian Wu, Dingjiang Huang, Jinchen Zhu, Hui Li, Qianru Xv, Tianle Liu, Gang Wu, Junpeng Jiang, Xianming Liu, Junjun Jiang, Mingjian Zhang, Shizhuang Weng, Jing Hu, Chengxu Wu, Qinrui Fan, Chengming Feng, Ziwei Luo, Shu Hu, Siwei Lyu, Xi Wu, Xin Wang:
NTIRE 2023 Challenge on Efficient Super-Resolution: Methods and Results. CVPR Workshops 2023: 1922-1960
2016
[c61]
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Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu:
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). ASP-DAC 2016: 139-146
[c60]
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Xing Wei, Yi Diao, Yu-Liang Wu:
To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. ASP-DAC 2016: 623-630
2015
[c59]
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Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu:
A coupling area reduction technique applying ODC shifting. DATE 2015: 1461-1466
[c58]
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Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu:
A universal macro block mapping scheme for arithmetic circuits. DATE 2015: 1629-1634
2014
[c57]
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Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu:
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. ACM Great Lakes Symposium on VLSI 2014: 233-234
[c56]
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Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. VLSID 2014: 375-380
2013
[c55]
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  - conf/aspdac/WeiTWSA13
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Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC 2013: 350-355
[c54]
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Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu:
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability. DFTS 2013: 71-76
2012
[c53]
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  - conf/arc/FanCW12
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Hongbing Fan, Yue-Ang Chen, Yu-Liang Wu:
R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip. ARC 2012: 365-371
[c52]
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Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. ASP-DAC 2012: 511-516
[c51]
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  - conf/date/YangLTW12
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Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu:
Almost every wire is removable: A modeling and solution for removing any circuit wire. DATE 2012: 1573-1578
[c50]
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Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI 2012: 327-332
2011
[c49]
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Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu:
On applying erroneous clock gating conditions to further cut down power. ASP-DAC 2011: 509-514
[c48]
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  - conf/cadgraphics/DiaoW11
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Yi Diao, Yu-Liang Wu:
A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions. CAD/Graphics 2011: 471-477
2010
[c47]
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  - conf/arc/FanWC10
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Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung:
Design Automation for Reconfigurable Interconnection Networks. ARC 2010: 244-256
[c46]
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  - conf/cocoa/FanW10
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Hongbing Fan, Yu-Liang Wu:
Structured Overlay Network for File Distribution. COCOA (2) 2010: 292-302
[c45]
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  - conf/dac/YangLW10
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Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu:
ECR: a low complexity generalized error cancellation rewiring scheme. DAC 2010: 511-516
[c44]
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  - conf/glvlsi/LamYTW10
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Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. ACM Great Lakes Symposium on VLSI 2010: 179-184
[c43]
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  - conf/iscas/YangXW10
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Xiaoqing Yang, Zigang Xiao, Yu-Liang Wu:
Improving redundancy addition and removal using unreachable states for sequential circuits. ISCAS 2010: 3172-3175
2009
[c42]
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  - conf/cocoa/FanW09
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Hongbing Fan, Yu-Liang Wu:
A New Approach for Rearrangeable Multicast Switching Networks. COCOA 2009: 384-394
2008
[c41]
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  - conf/cisse/XiongWJ08
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Control Circuitry for Self-Repairable MEMS Accelerometers. EIAT/IETA 2008: 265-270
[c40]
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  - conf/cocoa/FanHWE08
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Hongbing Fan, Christian Hundt, Yu-Liang Wu, Jason Ernst:
Algorithms and Implementation for Interconnection Graph Problem. COCOA 2008: 201-210
[c39]
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  - conf/dft/XiongWJ08
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Material Fatigue and Reliability of MEMS Accelerometers. DFT 2008: 314-322
[c38]
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  - conf/ersa/TangZW08
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Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu:
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. ERSA 2008: 116-121
[c37]
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Hongbing Fan, Yu-Liang Wu:
Interconnection Graph Problem. FCS 2008: 51-55
[c36]
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Hongbing Fan, Jason Ernst, Yu-Liang Wu:
Customized Reconfigurable Interconnection Networks for multiple application SOCS. FPL 2008: 491-494
2007
[c35]
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  - conf/dac/ZhouTLW07
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Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu:
How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. DAC 2007: 922-927
[c34]
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  - conf/iscas/TangLW07
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Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu:
Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. ISCAS 2007: 1049-1052
2006
[c33]
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  - conf/dft/XiongWJ06
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Reliability Analysis of Self-Repairable MEMS Accelerometer. DFT 2006: 236-244
2005
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Hongbing Fan, Yu-Liang Wu:
Crossbar based design schemes for switch boxes and programmable interconnection networks. ASP-DAC 2005: 910-915
[c31]
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Design and Analysis of Self-Repairable MEMS Accelerometer. DFT 2005: 21-32
[c30]
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Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang:
FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) 2005: 5653-5656
[c29]
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Yu-Liang Wu, Chi-Kong Chan:
On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems. SAGA 2005: 70-81
2004
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Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu:
Scan-Based BIST Using an Improved Scan Forest Architecture. Asian Test Symposium 2004: 88-93
[c27]
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Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu:
On Optimal Irregular Switch Box Designs. FPL 2004: 189-199
[c26]
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Yuen-Ting Wu, Yu-Liang Wu:
A Less Flexibility First Based Algorithm for the Container Loading Problem. OR 2004: 368-376
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Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. VTS 2004: 148-153
2003
[c24]
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Jiping Liu, Hongbing Fan, Yu-Liang Wu:
On improving FPGA routability applying multi-level switch boxes. ASP-DAC 2003: 366-369
[c23]
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Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu:
A cost-effective scan architecture for scan testing with non-scan test power and test application cost. DAC 2003: 744-747
2002
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Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On Optimum Designs of Universal Switch Blocks. FPL 2002: 142-151
2001
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Chin Ngai Sze, Yu-Liang Wu:
Improved alternative wiring scheme applying dominator relationship. ASP-DAC 2001: 473-478
[c20]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu:
Combinatorial routing analysis and design of universal switch blocks. ASP-DAC 2001: 641-644
[c19]
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Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On Optimum Switch Box Designs for 2-D FPGAs. DAC 2001: 203-208
[c18]
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Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng:
Further improve circuit partitioning using GBAW logic perturbation techniques. DATE 2001: 233-239
2000
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Wangning Long, Yu-Liang Wu, Jinian Bian:
IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC 2000: 415-422
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Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng:
Circuit partitioning with coupled logic restructuring techniques. ASP-DAC 2000: 655-660
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Hongbing Fan, Jiping Liu, Yu-Liang Wu:
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. ICCAD 2000: 93-98
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Hongbing Fan, Jiping Liu, Yu-Liang Wu:
A global routing model for universal switch box design. ICECS 2000: 78-81
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Yu-Liang Wu, Chin Ngai Sze, Chak-Chung Cheung, Hongbing Fan:
On improved graph-based alternative wiring scheme for multi-level logic optimization. ICECS 2000: 654-657
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Yu-Liang Wu, Wangning Long, Hongbing Fan:
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. VLSI Design 2000: 268-273
1999
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Jin Ding, Yu-Liang Wu:
On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. ASP-DAC 1999: 311-314
1998
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Jiaofeng Pan, Yu-Liang Wu, C. K. Wong:
On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. ASP-DAC 1998: 535-540
[c9]
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Yu-Liang Wu, Hongbing Fan, C. K. Wong:
On thin Boolean functions and related optimum OBDD ordering. ICCD 1998: 216-218
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Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330
1997
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Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama:
Not necessarily more switches more routability [sic.]. ASP-DAC 1997: 579-584
1995
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Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing on regular segmented 2-D FPGAs. ASP-DAC 1995
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Yu-Liang Wu, Malgorzata Marek-Sadowska:
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC 1995: 568-573
1994
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Yu-Liang Wu, Malgorzata Marek-Sadowska:
An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC 1994: 412-416
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Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
On computational complexity of a detailed routing problem in two dimensional FPGAs. Great Lakes Symposium on VLSI 1994: 70-75
[c2]
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Yu-Liang Wu, Douglas Chang:
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. ICCAD 1994: 362-366
1993
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Yu-Liang Wu, Malgorzata Marek-Sadowska:
Graph based analysis of FPGA routing. EURO-DAC 1993: 104-109

Parts in Books or Collections

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1999
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Wenqi Huang, Yu-Liang Wu, C. K. Wong:
A Cogitative Algorithm for Solving the Equal Circles Packing Problem. Handbook of Combinatorial Optimization 1999: 591-605

Coauthor Index

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