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Vasilis F. Pavlidis
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2020 – today
- 2024
- [c55]Krithika Dhananjay, Vasilis F. Pavlidis, Ayse K. Coskun, Emre Salman:
Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors. ISQED 2024: 1-7 - [c54]Vasiliki Gogolou, Thomas Noulis, Vasilis F. Pavlidis:
CMOS Charge Pump Design for Minimal Silicon Footprint. MOCAST 2024: 1-4 - [i3]Prachi Shukla, Vasilis F. Pavlidis, Emre Salman, Ayse K. Coskun:
A New Dataflow Implementation to Improve Energy Efficiency of Monolithic 3D Systolic Arrays. CoRR abs/2401.03585 (2024) - [i2]Dimitrios Garyfallou, Athanasios Stefanou, Christos Giamouzis, Moschos Antoniadis, Georgios Chararas, Konstantinos Chatzis, Dimitris Samaras, Rafaela Themeli, Anastasios Michailidis, Vasiliki Gogolou, Nikos Zachos, Nestor E. Evmorfopoulos, Thomas Noulis, Vasilis F. Pavlidis, Alkiviadis Hatzopoulos, Elpida Chatzineofytou, Yiannis Moisiadis:
MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits. CoRR abs/2401.10236 (2024) - 2023
- [j24]Prachi Shukla
, Vasilis F. Pavlidis
, Emre Salman
, Ayse K. Coskun
:
TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4350-4363 (2023) - [c53]Georgios Chararas, Athanasios Stefanou, Alkiviadis Hatzopoulos, Vasilis F. Pavlidis:
A Novel Design Methodology for Modular, Digitally Controlled, Multiband, mmWave LNAs. MOCAST 2023: 1-4 - [c52]Andreas Tsiougkos
, Alkis Hatzopoulos, Vasilis F. Pavlidis:
Mismatch Driven Systematic Design Methodology for Transistor Based Active Resistors. MWSCAS 2023: 619-623 - 2022
- [j23]Yuanqing Cheng
, Xiaochen Guo, Vasilis F. Pavlidis:
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective. Integr. 85: 97-107 (2022) - [j22]Eleni Maragkoudaki
, William B. Toms, Vasilis F. Pavlidis
:
Energy-Efficient Encoding for High-Speed Serial Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1484-1496 (2022) - [j21]Krithika Dhananjay
, Vasilis F. Pavlidis
, Ayse K. Coskun
, Emre Salman
:
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1654-1667 (2022) - [c51]Minmin Jiang, Eleni Maragkoudaki, Vasilis F. Pavlidis:
Mitigating EM Side-Channel Attacks with Dynamic Delay Insertion and Data Bus Inversion. ISCAS 2022: 1724-1728 - [c50]Baoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng:
Thermal Modeling and Design Exploration for Monolithic 3D ICs. ISQED 2022: 1-6 - [c49]Konstantinos Falis, Andreas Tsiougkos
, Vasilis F. Pavlidis:
Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems. VLSI-SoC 2022: 1-6 - [i1]Prachi Shukla, Vasilis F. Pavlidis, Emre Salman, Ayse K. Coskun:
Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications. CoRR abs/2203.15874 (2022) - 2021
- [j20]Fengjuan Wang, Lei Ke, Xiangkun Yin, Vasilis F. Pavlidis, Ningmei Yu, Yuan Yang:
TSV-based hairpin bandpass filter for 6G mobile communication applications. IEICE Electron. Express 18(15): 20210247 (2021) - [j19]Xiangkun Yin
, Fengjuan Wang
, Vasilis F. Pavlidis, Xiaoxian Liu
, Qijun Lu, Tao Zhang, Yang Liu:
Design of compact LC lowpass filters based on coaxial through-silicon vias array. Microelectron. J. 116: 105217 (2021) - [j18]Krithika Dhananjay, Prachi Shukla, Vasilis F. Pavlidis, Ayse K. Coskun
, Emre Salman
:
Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 837-843 (2021) - [c48]Prachi Shukla, Sean S. Nemtzow, Vasilis F. Pavlidis, Emre Salman
, Ayse K. Coskun
:
Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators. ASP-DAC 2021: 709-714 - [c47]Andreas Tsiougkos
, Vasilis F. Pavlidis:
A PWM-free DC-DC Boost Converter with 0.43 V Input for Extended Battery Use in IoT Applications. MWSCAS 2021: 479-483 - [c46]Minmin Jiang, Vasilis F. Pavlidis:
Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks. SLIP 2021: 25-32 - 2020
- [j17]Eleni Maragkoudaki
, Vasilis F. Pavlidis
:
Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2551-2562 (2020) - [c45]Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng:
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. ACM Great Lakes Symposium on VLSI 2020: 399-404 - [c44]Minmin Jiang, Ioannis A. Papistas, Vasilis F. Pavlidis:
Cost Modeling and Analysis of TSV and Contactless 3D-ICs. ACM Great Lakes Symposium on VLSI 2020: 519-524 - [c43]Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis:
Metal Stack and Partitioning Exploration for Monolithic 3D ICs. ISVLSI 2020: 398-403
2010 – 2019
- 2019
- [j16]Ioannis A. Papistas
, Vasilis F. Pavlidis
, Dimitrios Velenis:
Fabrication Cost Analysis for Contactless 3-D ICs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 758-762 (2019) - [j15]Przemyslaw Mroszczyk
, John Goodacre, Vasilis F. Pavlidis
:
Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1775-1779 (2019) - [j14]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
, Chip-Hong Chang
, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti
, Shiro Dosho, Rolf Drechsler
, Ibrahim Abe M. Elfadel
, Ruonan Han, Masanori Hashimoto
, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho
, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun
, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra
, Baker Mohammad
, Mehran Mozaffari Kermani
, Makoto Nagata
, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont
, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan
, Mark M. Tehranipoor, Aida Todri-Sanial
, Marian Verhelst
, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang
, Jun Zhou, Mark Zwolinski
, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c42]Chao Zhang, Milan Mihajlovic, Vasilis F. Pavlidis:
Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs. DATE 2019: 268-271 - [c41]Eleni Maragkoudaki
, Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Adaptive Word Reordering for Low-Power Inter-Chip Communication. DATE 2019: 980-983 - [c40]Konstantinos Maragos, George Lentaris, Dimitrios Soudris, Vasilis F. Pavlidis:
PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. FPGA 2019: 190 - [c39]Prachi Shukla, Ayse K. Coskun
, Vasilis F. Pavlidis, Emre Salman:
An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs. ACM Great Lakes Symposium on VLSI 2019: 439-444 - [c38]Charalampos Antoniadis
, Milan Mihajlovic, Nestor E. Evmorfopoulos, Georgios I. Stamoulis, Vasilis F. Pavlidis:
Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits. ICCD 2019: 405-408 - [e1]Farshad Firouzi, Krishnendu Chakrabarty, Bahar J. Farahani, Fangming Ye, Vasilis F. Pavlidis:
Proceedings of the International Conference on Omni-Layer Intelligent Systems, COINS 2019, Crete, Greece, May 5-7, 2019. ACM 2019, ISBN 978-1-4503-6640-3 [contents] - 2018
- [j13]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Contactless Heterogeneous 3-D ICs for Smart Sensing Systems. Integr. 62: 329-340 (2018) - [j12]Scott Ladenheim, Yi-Chung Chen
, Milan Mihajlovic, Vasilis F. Pavlidis
:
The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3123-3136 (2018) - [j11]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2547-2558 (2018) - [c37]Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Mismatch Compensation Technique for Inverter-Based CMOS Circuits. ISCAS 2018: 1-5 - [c36]Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Ultra-low swing CMOS transceiver for 2.5-D integrated systems. ISQED 2018: 262-267 - [c35]Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies. NANOARCH 2018: 124-130 - 2017
- [j10]Harry Kalargaris, Vasilis F. Pavlidis:
Voltage scaling for 3-D ICs: When, how, and how much? Microelectron. J. 69: 35-44 (2017) - [c34]Konstantinos Maragos, George Lentaris, Dimitrios Soudris
, Kostas Siozios
, Vasilis F. Pavlidis:
Application performance improvement by exploiting process variability on FPGA devices. DATE 2017: 452-457 - [c33]Yi-Chung Chen, Scott Ladenheim, Harry Kalargaris, Milan Mihajlovic, Vasilis F. Pavlidis:
Computationally efficient standard-cell FEM-based thermal analysis. ICCAD 2017: 490-495 - [c32]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Contactless inter-tier communication for heterogeneous 3-D ICs. ISCAS 2017: 1-4 - [c31]Harry Kalargaris, Yi-Chung Chen, Vasilis F. Pavlidis:
STA compatible backend design flow for TSV-based 3-D ICs. ISQED 2017: 186-190 - 2016
- [c30]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects. ACM Great Lakes Symposium on VLSI 2016: 257-262 - [c29]Scott Ladenheim, Yi-Chung Chen, Milan Mihajlovic, Vasilis F. Pavlidis:
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods. ICCAD 2016: 123 - [c28]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Crosstalk noise effects of on-chip inductive links on power delivery networks. ISCAS 2016: 1938-1941 - 2015
- [c27]Ioannis A. Papistas
, Vasilis F. Pavlidis:
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs. ECCTD 2015: 1-4 - 2014
- [c26]Paul W. Nutter, Vasilis F. Pavlidis, Jeffrey Pepper:
Efficient teaching of digital design with automated assessment and feedback. EWME 2014: 203-207 - [c25]Harry Kalargaris, Vasilis F. Pavlidis:
Interconnect design tradeoffs for silicon and glass interposers. NEWCAS 2014: 77-80 - 2013
- [j9]Somayyeh Rahimian, Vasilis F. Pavlidis, Xifan Tang, Giovanni De Micheli
:
An Enhanced Design Methodology for Resonant Clock Trees. J. Low Power Electron. 9(2): 198-206 (2013) - [j8]Hu Xu, Vasilis F. Pavlidis, Xifan Tang, Wayne P. Burleson, Giovanni De Micheli:
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2226-2239 (2013) - [c24]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli:
3.5-D integration: A case study. ISCAS 2013: 2087-2090 - 2012
- [j7]Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Effect of process variations in 3D global clock distribution networks. ACM J. Emerg. Technol. Comput. Syst. 8(3): 20:1-20:25 (2012) - [j6]Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli:
Inter-Plane Communication Methods for 3-D ICs. J. Low Power Electron. 8(2): 170-181 (2012) - [j5]Kostas Siozios
, Vasilis F. Pavlidis, Dimitrios Soudris
:
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric. ACM Trans. Reconfigurable Technol. Syst. 5(1): 4:1-4:23 (2012) - [c23]Cheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli:
Voltage propagation method for 3-D power grid analysis. DATE 2012: 844-847 - [c22]Vasilis F. Pavlidis, Hu Xu, Giovanni De Micheli:
Enhanced wafer matching heuristics for 3-D ICs. ETS 2012: 1 - [c21]Hu Xu, Vasilis F. Pavlidis, Wayne P. Burleson, Giovanni De Micheli:
The combined effect of process variations and power supply noise on clock skew and jitter. ISQED 2012: 320-327 - 2011
- [j4]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2256-2266 (2011) - [c20]Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Analytical heat transfer model for thermal through-silicon vias. DATE 2011: 395-400 - [c19]Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Skew variability in 3-D ICs with multiple clock domains. ISCAS 2011: 2221-2224 - [c18]Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman:
Clock distribution models of 3-D integrated systems. ISCAS 2011: 2225-2228 - [c17]Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli:
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. PATMOS 2011: 267-277 - [p1]Vasilis F. Pavlidis, Eby G. Friedman:
Physical Analysis of NoC Topologies for 3-D Integrated Systems. 3D Integration for NoC-based SoC Architectures 2011: 89-114 - 2010
- [c16]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli:
Performance analysis of 3-D monolithic integrated circuits. 3DIC 2010: 1-4 - [c15]Vasilis F. Pavlidis, Hu Xu, Ioannis Tsioutsios, Giovanni De Micheli:
Synchronization and power integrity issues in 3-D ICs. APCCAS 2010: 536-539 - [c14]Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli:
Physical design tradeoffs in power distribution networks for 3-D ICs. ICECS 2010: 430-433 - [c13]Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Process-induced skew variation for scaled 2-D and 3-D ICs. SLIP 2010: 17-24
2000 – 2009
- 2009
- [j3]Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proc. IEEE 97(1): 123-140 (2009) - [c12]Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris
:
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs. DATE 2009: 172-177 - [c11]Vasilis F. Pavlidis, Giovanni De Micheli:
Power distribution paths in 3-D ICS. ACM Great Lakes Symposium on VLSI 2009: 263-268 - [c10]Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. NanoNet 2009: 141-150 - 2008
- [j2]Vasilis F. Pavlidis, Eby G. Friedman:
Timing-driven via placement heuristics for three-dimensional ICs. Integr. 41(4): 489-508 (2008) - [c9]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock distribution networks for 3-D ictegrated Circuits. CICC 2008: 651-654 - [c8]Vasilis F. Pavlidis, Eby G. Friedman:
Physical Design Issues in 3-D Integrated Technologies. VLSI-SoC (Selected Papers) 2008: 1-21 - 2007
- [j1]Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1081-1090 (2007) - [c7]Kostas Siozios
, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris
:
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. FPL 2007: 652-655 - [c6]Kostas Siozios
, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris
:
A software-supported methodology for designing high-performance 3D FPGA architectures. VLSI-SoC 2007: 54-59 - 2006
- [c5]Vasilis F. Pavlidis, Eby G. Friedman:
Via placement for minimum interconnect delay in three-dimensional (3D) circuits. ISCAS 2006 - [c4]Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. SoCC 2006: 285-288 - 2005
- [c3]Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs. ACM Great Lakes Symposium on VLSI 2005: 20-25 - 2003
- [c2]Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis:
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132 - 2001
- [c1]Dimitrios Soudris, Vasilis F. Pavlidis, Adonios Thanailakis:
Designing low-power energy recovery adders based on pass transistor logic. ICECS 2001: 777-780
Coauthor Index
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