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ORCID16th ATS 2007: Beijing, China
- 16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007. IEEE 2007, ISBN 0-7695-2890-2
- Jacob Abraham:
Keynote Speech 1: New Paths for Test. 3 - Sanjiv Taneja:
Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test. 4-5 - T. M. Mak:
Invited Talk 1: Testing of Power Constraint Computing. 6 - T. W. Williams:
Invited Talk 2: EDA to the Rescue of the Silicon Roadmap. 7-8 - Kary Chien:
Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology. 9 - Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil:
The Region-Exhaustive Fault Model. 13-18 - Weixin Wu, Michael S. Hsiao:
Mining Sequential Constraints for Pseudo-Functional Testing. 19-24 - Irith Pomeranz, Praveen Parvathala, Srinivas Patil:
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. 25-32 - Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Fast Bridging Fault Diagnosis using Logic Information. 33-38 - Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. 39-44 - Ruifeng Guo
, Yu Huang, Wu-Tung Cheng:
Fault Dictionary Based Scan Chain Failure Diagnosis. 45-52 - Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu:
Test Education in the Global Economy. 53 - Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. 57-64 - Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara:
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. 65-68 - Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen:
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. 69-72 - Elham K. Moghaddam, Shaahin Hessabi:
An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits. 73-78 - Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar:
A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding. 79-86 - Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue:
Test Compression / Decompression Based on JPEG VLC Algorithm. 87-90 - Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani:
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos. 91-94 - Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li:
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. 95-100 - Urban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod:
Resistive Bridging Faults DFT with Adaptive Power Management Awareness. 101-106 - Dan Zhao, Ronghua Huang, Hideo Fujiwara:
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE. 107-110 - Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang:
An Efficient Peak Power Reduction Technique for Scan Testing. 111-114 - Sunghoon Chun, YongJoon Kim, Sungho Kang:
High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects. 115-120 - Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich:
A RTL Testability Analyzer Based on Logical Virtual Prototyping. 121-124 - Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya:
Optimum Test Set for Bridging Fault Detection in Reversible Circuits. 125-128 - Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li:
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. 129-134 - Hung-Kai Chen, Chauchin Su:
A Test and Diagnosis Methodology for RF Transceivers. 135-138 - Ganesh Srinivasan, Abhijit Chatterjee, Vishwanath Natarajan:
Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources. 139-142 - Hsieh-Hung Hsieh, Yen-Chih Huang, Liang-Hung Lu, Guo-Wei Huang:
A BIST Technique for RF Voltage-Controlled Oscillators. 143-148 - Feng-An Qian, Jian-Hui Jiang:
An Improved Test Case Generation Method of Pair-Wise Testing. 149-154 - Monalisa Sarma, Rajib Mall:
System Testing using UML Models. 155-158 - Shiyi Xu:
Reconsideration of Software Reliability Measurements. 159-164 - Haihua Shen, Heng Zhang:
An Accurate Analysis of Microprocessor Design Verification. 165-171 - Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi:
Optimized Assignment Coverage Computation in Formal Verification of Digital Systems. 172-177 - Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao:
EHSAT Modeling from Algorithm Description for RTL Model Checking. 178-186 - Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. 187-192 - Jaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park:
Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC. 193-198 - Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara:
Test Scheduling for Memory Cores with Built-In Self-Repair. 199-206 - Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian:
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. 207 - Yu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong:
IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy. 211 - Wataru Kawamura, Takeshi Onodera:
Experimental Results of Transition Fault Simulation with DC Scan Tests. 212 - Brion L. Keller, Tom Jackson, Anis Uzzaman:
A Review of Power Strategies for DFT and ATPG. 213 - Shawn Molavi, Toby McPheeters:
Concurrent Test Implementations. 214 - Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg:
Scan Diagnosis and Its Successful Industrial Applications. 215 - Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement. 219-223 - Dongwoo Hong, Kwang-Ting Cheng:
An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing. 224-229 - Xinsong Zhang, Simon S. Ang, Chandra Carter:
Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods. 230-238 - Florence Azaïs, Laurent Larguier, Michel Renovell:
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits. 239-244 - Chunsheng Liu, Yang Wu, Yu Huang:
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis. 245-250 - Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane:
Low Power Reduced Pin Count Test Methodology. 251-258 - Minjin Zhang, Xiaowei Li:
Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects. 259-264 - Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker:
Simulating Open-Via Defects. 265-270 - Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. 271-274 - Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara:
Fault-dependent/independent Test Generation Methods for State Observable FSMs. 275-280 - Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou:
Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead. 281-287 - Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna:
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. 288-294 - Yu Huang, Xijiang Lin:
Programmable Logic BIST for At-speed Test. 295-300 - Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Targeting Equivalence Classes. 301-306 - Mingjing Chen, Alex Orailoglu:
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements. 307-312 - Shijian Zhang, Weiwu Hu:
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors. 313-318 - Ramashis Das, John P. Hayes:
Monitoring Transient Errors in Sequential Circuits. 319-322 - Shaohua Lei, Yinhe Han, Xiaowei Li:
Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic. 323-328 - Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara:
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. 329-334 - Gefu Xu, Adit D. Singh:
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. 335-340 - Xiaoxin Fan, Yu Hu, Laung-Terng Wang:
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. 341-348 - Li-Ming Denq, Cheng-Wen Wu:
A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. 349-354 - Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu:
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. 355-360 - Jochen Rivoir:
Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2). 361-366 - Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera:
Test Roles in Diagnosis and Silicon Debug. 367 - Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht:
Programmable Scan-Based Logic Built-In Self Test. 371-377 - Livier Lizarraga, Salvador Mir, Gilles Sicard:
Evaluation of a BIST Technique for CMOS Imagers. 378-383 - Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang:
Built-In Speed Grading with a Process-Tolerant ADPLL. 384-392 - Selim Sermet Akbay, Shreyas Sen, Abhijit Chatterjee:
Testing RF Components with Supply Current Signatures. 393-398 - Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura:
Current Testable Design of Resistor String DACs. 399-403 - Liquan Fang, Yang Zhong, H. van de Donk, Yizi Xing:
Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC. 404-412 - Nan-Cheng Lai, Sying-Jyan Wang:
Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs. 413-418 - Chandan Giri, Pradeep Kumar Choudhary, Santanu Chattopadhyay:
Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering. 419-424 - Bo-Hua Chen, Wei-Chung Kao, Bing-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li:
Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique. 425-432 - Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker:
SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. 433-438 - Jian Kang, Sharad C. Seth, Shashank K. Mehta:
Symbolic Path Sensitization Analysis and Applications. 439-444 - Stephan Eggersglüß, Rolf Drechsler:
Improving Test Pattern Compactness in SAT-based ATPG. 445-452 - Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi:
An HDL-Based Platform for High Level NoC Switch Testing. 453-458 - Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. 459-462 - Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You:
Test Efficiency Analysis and Improvement of SOC Test Platforms. 463-466 - Lei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang:
Block Marking and Updating Coding in Test Data Compression for SoC. 467-472 - Choon-Sang Chew:
Issues Regarding New Product Release in Semiconductor Manufacturing. 473 - Akinori Maeda:
How the noise floor affects the production yield. 474 - Sean Lu, Dee-Won Lee:
Integrated Test Solution for embedded UHF/RF SOC. 475 - Friedrich Taenzler:
Production Test of High Volume Commercial RFIC. 476 - Irith Pomeranz, Sudhakar M. Reddy:
Enhanced Broadside Testing for Improved Transition Fault Coverage. 479-484 - I-De Huang, Sandeep K. Gupta:
On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis. 485-492 - Xijiang Lin, Mark Kassab, Janusz Rajski:
Test Generation for Timing-Critical Transition Faults. 493-500 - Jin-Fu Li:
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells. 501-506 - Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel:
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. 507-510 - Jenny Fan, Xiao-Yu Li, Ismed Hartanto:
Using FPGA configuration memory to accelerate yield learning for advanced process. 511-516 - David Bement, David Karr:
Bluetooth Hopping BER Testing Methodologies on a Production Test Platform. 517 - Deng Yue:
Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC. 518 - Takahiro J. Yamaguchi:
Top 5 Issues in Practical Testing of High-Speed Interface Devices. 519 - Fidel Muradali, Jochen Rivoir:
Special Session: Analog Production Test. 523
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