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ORCIDITC 2025: San Diego, CA, USA
- IEEE International Test Conference, ITC 2025, San Diego, CA, USA, September 20-26, 2025. IEEE 2025, ISBN 979-8-3315-7041-5
- Seoyeon Kim, Yu Su, Li-C. Wang:
IEA-Plugin: An AI Agent Reasoner for Test Data Analytics. 1-10 - Stephen Sunter, Krzysztof Jurga:
Scan Test for 99% Defect Coverage of R-2R DACs. 11-18 - Hao-Yu Yang, Hsin-Wei Hung, Nan-Hsin Tseng:
Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2. 19-26 - Quan Cheng, Hao-Yang Chi, Chien-Hsing Liang, Yu-Hong Chao, Huizi Zhang, Yuan Liang, Mingtao Zhang, Wang Liao, Jinjun Xiong, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin:
Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis. 27-36 - Po-Yao Chuang, Erik Jan Marinissen:
Chiplets' Die-to-Die Interconnect Repair Language (IRL). 37-44 - Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li:
TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. 45-52 - Jiaming Wu, Domenic Forte:
QuEST: Quantitative Entropy based Security and Trojan Detection Framework for Confidentiality Verification. 53-62 - Minoru Iida, Norio Kobayashi, Hideki Shirasu, Masayuki Nakamura:
Push-on mating 57- to 81- GHz mm-Wave interface with high repeatability for ATE application. 63-71 - Cheng-En Chung, Jun-Han Jian, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang, Dong-Yi Chen:
Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion. 72-81 - Szczepan Urban, Jakub Janicki, Piotr Zimnowlodzki, Artur Stelmach, Manish Sharma:
Chain Cell-Aware Diagnosis. 82-91 - Jeffery Y.-C. Chen, Jason W.-Y. Cheng, Aaron C.-W. Liang, Charles H.-P. Wen, Gung-Yu Pan, Hen-Ming Lin:
Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions. 92-101 - Shubhendu Shrivastava, Jo Gunnes, Anteneh Gebregiorgis, Said Hamdioui:
Stress Aware Quiescent Current Test Optimization. 102-110 - Jan Burchard, Matthias Kampmann, Ayush Patel, Marta Stepniewska, Przemyslaw Szymanski, Wojciech Janiszewski, Jean-François Côté, Michal Olejarz, Olga Przybysz, Lori Schramm, Jonathan Gaudet, Martin Keim:
Persistent High-Bandwidth IJTAG Data Delivery. 111-120 - Peter Domanski, Deepesh Sahoo, Eduardo Ortega, Farshad Firouzi, Krishnendu Chakrabarty:
LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale. 121-130 - Eduardo Ortega, Arjun Hati, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty:
OCTANE: On-Chip Telemetry-based Anomaly Notification Engine. 131-140 - Mohammed Zine E. Brahmi, Jennifer Dworak, Martina Perkovic, Megan Appel, Saidapet Ramesh, Ravi J. N, Ramanath Dharmavarm, Arun Kumar Anjaneyareddy, Chen He:
LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Pattern Generation for Zero Defect Automotive Designs. 141-150 - Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Automated Selection of Optimal EDT Input Configuration. 151-160 - Xuanyi Tan, Gitanjali Mukherjee, Dhruv Thapar, Arjun Chaudhuri, Sanmitra Banerjee, Rubin A. Parekhji, Krishnendu Chakrabarty:
NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical Applications. 161-170 - Hiroyuki Iwata, Sandeep Kumar Goel, Ankita Patidar, Fumiaki Takashima, Frank Lee:
A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) Applications. 171-180 - Min-Kyu Kim, Incheol Nam, Minju Shin, Kyungrak Cho, Gijong Sung, Deasun Kim, Heeil Hong, SangJoon Hwang:
A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM. 181-185 - Chien-Hsing Liang, Yu-Hong Chao, Jing-Jia Liou, Harry H. Chen:
A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis. 186-195 - Min-Hsin Liu, Ding-Wei Cheng, James Chien-Mo Li, Chris Nigh, Szu Huat Goh, Mason Chern, Bing-Han Hsieh, Subhadip Kundu:
Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up. 196-205 - Youngseok Son, Muyun Cho, Hyunyul Lim, Jaeseok Park, Piotr Zimnowlodzki, Szczepan Urban, Jayant D'Souza, Manish Sharma:
Advanced fault model, diagnosis and applications for deep nanometer process. 206-212 - Ali Nezhadi, Odysseas Chatzopoulos, Mahta Mayahinia, George Papadimitriou, Mehdi Baradaran Tahoori, Dimitris Gizopoulos:
Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures. 213-222 - Dina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori:
Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints. 223-232 - Behnam Farnaghinejad, Davide Bellizia, Alessandra Dolmeta, Guido Masera, Antonio Porsia, Annachiara Ruospo, Stefano Di Carlo, Alessandro Savino, Ernesto Sánchez:
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF). 233-242 - Sebastian Huhn, Matthias Kampmann, Jan Burchard, Reinhard Meier, Kacper Czerniawski, Lori Schramm, Sandipan Sharma, Nikita Naresh, Wilson Pradeep, Prachi Sinha, Mayank Parasrampuria, Jonathan Gaudet, Martin Keim:
Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks. 243-252 - Suriyaprakash Natarajan, Chaitali S. Oak, Nipun Chaplot, Vijay Kakollu, Venkata A. R. Gurram, Manish J. Mishra, Fayez Abu-gosh:
DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors. 253-261 - Lawrence M. Schlitt, Pratishtha Agnihotri, Priyank Kalla, Steve Blair:
Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning. 262-271 - Uma Srinivasan, William V. Huott, Austen Hall, Ryan Thorpe, Daniel Rodko, Greg Hornicek, Brian Noble:
Ultra dense SRAM Cell Test Challenges. 272-280 - Gowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha:
Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance. 281-290 - Hans Martin von Staudt, Jeff Rearick, Michael Laisne:
Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges. 291-300 - Chris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. (Shawn) Blanton:
IC-PEPR: PEPR Testing Goes Intra-Cell. 301-309 - Partho Bhoumik, Dhruv Thapar, Arjun Chaudhuri, Krishnendu Chakrabarty:
SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages*. 310-319 - Soyed Tuhin Ahmed, Eduardo Ortega, Ryan Depsey, T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Matthew J. Marinella, Krishnendu Chakrabarty:
Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation. 320-329 - Sandeep Kumar Goel, Ankita Patidar, Yue Tian, Frank Lee:
Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost. 330-338 - Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia:
LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency. 339-348 - Yuxuan Yin, Rebecca Chen, Boxun Xu, Chen He, Peng Li:
Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing. 349-356 - Partho Bhoumik, Arjun Chaudhuri, Sandeep Kumar Goel, Krishnendu Chakrabarty:
Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging*. 357-366 - Wu-Tung Cheng, Manish Sharma, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza:
Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects. 367-376 - Ravi J. N, Stephen Traynor:
'Shifting-left' Zero Defect Scan Test Development to Launch Automotive PPM-ready Products. 377-381 - Saghir A Shaikh, Brandon Brea, Gaurav Devrani, Muhammad Waheed, Lay Hoon Loh, Prakash Palanisamy, Jim Lee, Giyoung Yang:
Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing. 382-386 - Srimaiyee Pentyala, Stephen Traynor:
Full Enablement of Very-Low Voltage Testing to Deliver Zero Defect Quality Automotive Products. 387-391 - Dale Meehl, Sameer Chillarige, Bharath Nandakumar, Carl Wisnesky, Krishna Chakravadhanula:
Pseudo-Random Low Power Built In Self Test. 392-396 - Emmanuel Nti Darko, Saeid Karimpour, Ekaniyere Oko-Odion, Godfred Bonsu, Degang Chen:
Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering. 397-401 - Irith Pomeranz:
Functional Logic Diagnosis with Observation Points on Next-State Variables. 402-405 - Luc Romain, Roger Mah, Katarzyna Wojnowska, Albert Au, Lori Schramm:
Early Testing of Memory Redundant Row Elements. 406-409 - Changhao Wang, Sicong Yuan, Nima Kolahimahmoudi, Hanzhi Xun, Nicolò Bellarmino, Danyang Chen, Chujun Yin, Mottaqiallah Taouil, Moritz Fieback, Xiuyan Li, Lin Wang, Chaobo Li, Riccardo Cantoro, Said Hamdioui:
Device-Aware Test for Threshold Voltage Shifting in FeFET. 410-413 - Bin Du, Nehal Patel, Yerong Chen, Jeremy Chin, Katherine Tian:
Scan Strategies for High Quality Latch Array Testing. 414-417 - Reza Khoshzaban, Iacopo Guglielminetti, Michelangelo Grosso, Matteo Sonza Reorda, Riccardo Cantoro:
Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation. 418-421 - Anand Venkatachalam, Ernst Aderholz, Matthias Sauer, Simon Schweizer, Matthias Werner, Ilia Polian:
Influence of Automated Test Equipment Drift on Process Capability Studies. 422-425 - Aric Fowler, Carl Sechen, Yiorgos Makris:
An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists. 426-429 - Noeël Moeskops, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil:
Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflections. 430-433 - Shakil Ahmed, Dipali Jain, Kaveh Shamsi:
Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis. 434-437 - Krishna Prasad Gnawali, Andrea Costa, Nathalie Etono, Denis Martin, Bala Tarun Nelapatla, Amit Purohit:
Test Pattern Aware Streaming Fabric-based Scan Test Methodology. 438-441 - Vivek Chickermane, Marcel Zak, Mat O'Donnell:
Embedded Trace: A Key Enabler for Silicon Lifecycle Management. 442-445 - Riccardo Vettori, Alessia Galli:
Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment. 446-449 - Xun Jiao, Sunny Yang, Suman Gumudavelli, Shreya Varshini, Abhinav Pandey, Abhinav Jauhri, Francesco Caggioni, Gautham Vunnam, Harish Dattatraya Dixit, Jason Liang, Philip Henzler, Sameeksha Gupta, Tyler Graf, Venkat Ramesh, Fan Fred Lin:
CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption. 450-453 - Varun Sehgal, Subramanian Mahadevan, Ashrith S. Harith, Mohit Sharma, Saket Goyal, Nilanjan Mukherjee:
In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs. 454-457 - Kentaroh Katoh, Toru Nakura, Haruo Kobayashi:
High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops. 458-461 - Yutao Sun, Jiehua Huang, Xiangping Liao, Zhijun Wang, Liping Liang:
Graph Attention Networks Based Fault Prediction Framework for Functional Safety Verification. 462-465 - Sean Chen, Amarildo Garcia, Frank Chang, Joe Obedowski, Victor Castillo:
Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems? 466-469 - Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Annachiara Ruospo:
Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction. 470-473 - Joel Åhlund, Markus Törmänen, Erik Larsson:
Secure and Efficient Sharing of On-Chip Resources. 474-477 - Javad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash, Naghmeh Karimi:
FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks. 478-481 - Li Zhou, Menglong Lu, Li Luo, Jianfeng Zhang, Junbo Tie:
STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification. 482-485 - Sourav Roy, Domenic Forte:
MUX-based Polymorphic Registers and FSMs to Protect Roots of Trust from Voltage Fault Injection. 486-489 - Christos Vasileiou, Yiorgos Makris:
Teaching Llamas to Test: A Language-Based Approach. 490-493 - Po-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang, Jing-Jia Liou:
Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks. 494-497 - Ernesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Michael Glaß:
Early Reliability Estimation in Hardware Accelerators using Improved Colored Petri Nets. 498-501 - Seongkwan Lee, Hyuntae Jeong, Cheolmin Park, Jun Yeon Won, Minho Kang, Jaemoo Choi:
Method for Diagnosing Clock Jitter Using FPGA. 502-505 - Emmanouil Anastasios Serlis, Hanzhi Xun, Emmanouil Arapidis, Anteneh Gebregiorgis, Mottaqiallah Taouil, Said Hamdioui, Moritz Fieback:
Combined Array and ADC Structural Test for RRAM-based Multiply-and-Accumulate Circuits. 506-509 - Chen He, Rebecca Chen, Patrick Goertz:
Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training. 510-513 - Deepesh Sahoo, Eduardo Ortega, Peter Domanski, Farshad Firouzi, Krishnendu Chakrabarty:
TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption *. 514-517 - Dhruv Thapar, Arjun Chaudhuri, Kai Ni, Krishnendu Chakrabarty:
FeTest: Defect Analysis and March Test Solution for FeFETs *. 518-521 - Iresh M. Jayawardana, Krishna Dahal, Spyros Tragoudas, Khader S. Abdel-Hafez, Danushka Senarathna:
Deep Learning-based IC Monitoring. 522-525 - Saeid Karimpour, Emmanuel Nti Darko, Degang Chen:
An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Analog Circuits. 526-529 - Ragad Al-Huq, Yuegui Zheng:
Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping. 530-533 - Cao Wang, Shengbo Liu, Ming Cheng, Yindong Xiao, Xiaochun Li, David Keezer:
Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals. 534-537 - Shengbo Liu, Yindong Xiao, Cao Wang, Xiaochun Li, David Keezer:
FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals. 538-541 - Jyotika Suri, Rakesh Kinger, Sridhar Nimmagadda, Henry Fei:
Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access. 542-545 - Sridutt Tummalapalli, Srinath Reddy Yerakondappagari:
Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions. 546-549 - Vivek Chickermane, Marcel Zak, Mat O'Donnell:
Embedded Trace: A Key Enabler for Silicon Lifecycle Management. 550-553 - Jonathon E. Colburn, Peter Wohl, John A. Waicukauski, Yasunari Kanzawa:
Hybrid Static Learning for ATPG. 554-557 - Gabriele Filipponi:
FSWGEN: a Device-tree Specification driven System-Level Test workload generator. 558-559 - Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco:
A Benchmark Suite to Evaluate DNN's Resilience. 560-562 - Sudipta Paria:
LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs. 563-565 - Nicola Di Gruttola Giardino:
A Novel Tester-Based Approach for Functional Testing of Hardware Timers. 566-567 - Francesco Angione, Paolo Bernardi, Riccardo Cantoro:
System-Level Test techniques for Automotive SoCs. 568-577 - Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen:
Chiplet Interconnect Test and Repair. 578-587 - Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi:
Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time. 588-598 - Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan:
Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack. 599-608
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last updated on 2025-12-23 00:31 CET by the dblp team
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