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ORCIDJosé Monteiro 0001
José C. Monteiro 0001 – José Carlos Alves Pereira Monteiro
Person information
- affiliation: University of Lisbon, Portugal
- affiliation (former, PhD 1996): Massachusetts Institute of Technology, Cambridge, MA, USA
Other persons with the same name
- José Monteiro (aka: Jose Monteiro) — disambiguation page
- José Monteiro 0002
![[0000-0002-9000-9660]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-9000-9660")
(aka: José António dos Santos Fernandes Monteiro) — University of Coimbra, Department of Informatics Engineering, Portugal - José Monteiro 0003 (aka: José A. Monteiro) — Instituto Superior Politécnico Gaya (ISPGaya), Vila Nova de Gaia, Portugal
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2020 – today
- 2024
[j31]Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro:
A stochastic method for solving time-fractional differential equations. Comput. Math. Appl. 159: 240-253 (2024)- [j30]Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro:
A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. J. Sci. Comput. 99(2): 41 (2024) - [i8]Inês A. Ferreira, Juan A. Acebrón, José Monteiro:
Survey of a Class of Iterative Row-Action Methods: The Kaczmarz Method. CoRR abs/2401.02842 (2024) - [i7]Inês A. Ferreira, Juan A. Acebrón, José Monteiro:
Parallelization Strategies for the Randomized Kaczmarz Algorithm on Large-Scale Dense Systems. CoRR abs/2401.17474 (2024) - 2023
- [j29]Leonardo L. de Oliveira, Gabriel H. Eisenkraemer, Everton Alceu Carara, João B. Martins, José Monteiro:
Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations. ACM Trans. Sens. Networks 19(2): 36:1-36:39 (2023) - [i6]Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro:
A Stochastic Method for Solving Time-Fractional Differential Equations. CoRR abs/2303.15458 (2023) - [i5]Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro:
A Fast Monte Carlo algorithm for evaluating matrix functions with application in complex networks. CoRR abs/2308.01037 (2023) - 2022
- [j28]Filipe Magalhães, José Monteiro, Juan A. Acebrón, José R. Herrero:
A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks. Future Gener. Comput. Syst. 127: 320-330 (2022) - [j27]Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte:
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14(5): 1258 (2022) - [c80]Orestis Korakitis, Simon Garcia De Gonzalo, Nicolas L. Guidotti, João Pedro Barreto, José C. Monteiro, Antonio J. Peña:
Towards OmpSs-2 and OpenACC interoperation. PPoPP 2022: 433-434 - [c79]Orestis Korakitis, Simon Garcia de Gonzalo, Nicolas L. Guidotti, João Barreto, José Monteiro, Antonio J. Peña:
OmpSs-2 and OpenACC Interoperation. WACCPD@SC 2022: 11-21 - [i4]Roman Iakymchuk, Amândio Faustino, Andrew P. J. Emerson, João Barreto, Valeria Bartsch, Rodrigo Rodrigues, José C. Monteiro:
Efficient and Eventually Consistent Collective Operations. CoRR abs/2203.17063 (2022) - 2021
- [c78]Nicolas L. Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña:
Particle-In-Cell Simulation Using Asynchronous Tasking. Euro-Par 2021: 482-498 - [c77]Roman Iakymchuk, Amândio Faustino, Andrew P. J. Emerson, João Barreto, Valeria Bartsch, Rodrigo Rodrigues, José C. Monteiro:
Efficient and Eventually Consistent Collective Operations. IPDPS Workshops 2021: 621-630 - [i3]Nicolas L. Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña:
Particle-In-Cell Simulation using Asynchronous Tasking. CoRR abs/2106.12485 (2021) - [i2]Miguel Marques, Ilia Kuzmin, João Barreto, José Monteiro, Rodrigo Rodrigues:
Dynamic Page Placement on Real Persistent Memory Systems. CoRR abs/2112.12685 (2021) - 2020
- [j26]Juan A. Acebrón, José R. Herrero, José Monteiro:
A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method. Comput. Math. Appl. 79(12): 3495-3515 (2020) - [j25]Ahmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro, Paulo F. Flores:
Radix-2 r recoding with common subexpression elimination for multiple constant multiplication. IET Circuits Devices Syst. 14(7): 990-994 (2020) - [c76]Rafael Santos, João Afonso, José Monteiro:
Short-circuit Analysis using a Parallel QBF Solver. DCIS 2020: 1-6
2010 – 2019
- 2019
- [e3]Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 500, Springer 2019, ISBN 978-3-030-15662-6 [contents] - 2018
- [b2]Guilherme Arroz, José Monteiro, Arlindo L. Oliveira:
Computer Architecture - Digital Circuits to Microprocessors. WorldScientific 2018, ISBN 9789813238336, pp. 1-752 - 2017
- [c75]João Afonso, José Monteiro:
Analysis of short-circuit conditions in logic circuits. DATE 2017: 824-829 - [c74]Ahmed Liacha, Abdelkrim Kamel Oudjida, Farid Ferguene, José Monteiro, Paulo F. Flores:
A variable RADIX-2r algorithm for single constant multiplication. NEWCAS 2017: 265-268 - 2016
- [j24]Levent Aksoy, Paulo F. Flores, José Monteiro:
A novel method for the approximation of multiplierless constant matrix vector multiplication. EURASIP J. Embed. Syst. 2016: 12 (2016) - [j23]Nuno P. Lopes, José Monteiro:
Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic. Int. J. Softw. Tools Technol. Transf. 18(4): 359-374 (2016) - 2015
- [j22]Levent Aksoy, Paulo F. Flores, José Monteiro:
Exact and Approximate Algorithms for the Filter Design Optimization Problem. IEEE Trans. Signal Process. 63(1): 142-154 (2015) - [j21]Diogo Brito, Taimur Gibran Rabuske, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Quaternary Logic Lookup Table in Standard CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 306-316 (2015) - [c73]Levent Aksoy, Paulo F. Flores, José Monteiro:
A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication. EUC 2015: 98-105 - [c72]Levent Aksoy, Paulo F. Flores, José Monteiro:
Approximation of multiple constant multiplications using minimum look-up tables on FPGA. ISCAS 2015: 2884-2887 - 2014
- [j20]Levent Aksoy, Paulo F. Flores, José Monteiro:
A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst. Signal Process. 33(6): 1689-1719 (2014) - [j19]Levent Aksoy, Paulo F. Flores, José Monteiro:
Multiplierless Design of Folded DSP Blocks. ACM Trans. Design Autom. Electr. Syst. 20(1): 14:1-14:24 (2014) - [c71]Levent Aksoy, Paulo F. Flores, José Monteiro:
Optimization of design complexity in time-multiplexed constant multiplications. DATE 2014: 1-4 - [c70]Levent Aksoy, Paulo F. Flores, José Monteiro:
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. ICCD 2014: 42-47 - [c69]Levent Aksoy, Paulo F. Flores, José Monteiro:
ECHO: A novel method for the multiplierless design of constant array vector multiplication. ISCAS 2014: 1456-1459 - [c68]Nuno P. Lopes, José Monteiro:
Weakest Precondition Synthesis for Compiler Optimizations. VMCAI 2014: 203-221 - 2013
- [j18]José C. Costa, José C. Monteiro:
Coverage-directed observability-based validation for embedded software. ACM Trans. Design Autom. Electr. Syst. 18(2): 19:1-19:20 (2013) - [j17]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 498-511 (2013) - [c67]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Exploration of tradeoffs in the design of integer cosine transforms for image compression. ECCTD 2013: 1-4 - [c66]Levent Aksoy, Paulo F. Flores, José Monteiro:
SIREN: a depth-first search algorithm for the filter design optimization problem. ACM Great Lakes Symposium on VLSI 2013: 179-184 - [c65]Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Standard CMOS voltage-mode QLUT using a clock boosting technique. NEWCAS 2013: 1-4 - [c64]Leandro Zafalon Pieper, Eduardo A. C. da Costa, José C. Monteiro:
Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers. SBCCI 2013: 1-6 - [c63]Nuno P. Lopes, José Monteiro:
Automatic Equivalence Checking of UF+IA Programs. SPIN 2013: 282-300 - [c62]Levent Aksoy, Paulo F. Flores, José Monteiro:
Towards the least complex time-multiplexed constant multiplication. VLSI-SoC 2013: 328-331 - 2012
- [j16]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. 45(3): 294-306 (2012) - [j15]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17(1): 3:1-3:27 (2012) - [c61]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of low-complexity digital finite impulse response filters on FPGAs. DATE 2012: 1197-1202 - [c60]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Multiple tunable constant multiplications: Algorithms and applications. ICCAD 2012: 473-479 - [c59]Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Design and characterization of a QLUT in a standard CMOS process. ICECS 2012: 288-291 - [c58]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS 2012: 657-660 - [c57]João Bispo, João M. P. Cardoso, José Monteiro:
Hardware pipelining of runtime-detected loops. SBCCI 2012: 1-6 - 2011
- [j14]Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. 7(2): 294-301 (2011) - [j13]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocess. Microsystems 35(8): 729-741 (2011) - [c56]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD 2011: 588-591 - [c55]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66 - [c54]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI 2011: 79-84 - [c53]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS 2011: 567-570 - [c52]Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740 - [c51]Leonardo L. de Oliveira, Gustavo Fernando Dessbesell, João B. Martins, José Monteiro:
Hardware implementation of a centroid-based localization algorithm for mobile sensor networks. ISCAS 2011: 2829-2832 - [c50]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Multiplierless Design of Linear DSP Transforms. VLSI-SoC (Selected Papers) 2011: 73-93 - [c49]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153 - 2010
- [j12]Leandro Zafalon Pieper, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Sergio Bampi, José C. Monteiro:
Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers. J. Comput. 5(10): 1502-1509 (2010) - [c48]Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE 2010: 1797-1802 - [c47]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10 - [c46]Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862 - [c45]Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS 2010: 869-872 - [c44]Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS 2010: 84-93 - [c43]Leonardo Londero de Oliveira, João Baptista dos Santos Martins, Gustavo Fernando Dessbesell, José Monteiro:
CentroidM: a centroid-based localization algorithm for mobile sensor networks. SBCCI 2010: 204-209 - [c42]Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José Monteiro:
Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297 - [e2]José Monteiro, Rene van Leuken:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers. Lecture Notes in Computer Science 5953, Springer 2010, ISBN 978-3-642-11801-2 [contents] - [i1]Nuno P. Lopes, Levent Aksoy, Vasco Manquinho, José Monteiro:
Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability. CoRR abs/1011.2685 (2010)
2000 – 2009
- 2009
- [c41]José C. Costa, José C. Monteiro:
A MILP-based approach to path sensitization of embedded software. DATE 2009: 1568-1571 - [c40]António Gusmão, L. Miguel Silveira, José Monteiro:
Parameter tuning in SVM-based power macro-modeling. ISQED 2009: 135-140 - [c39]Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro:
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. PATMOS 2009: 297-306 - [c38]António Gusmão, Luís Miguel Silveira, José Monteiro:
Power Macro-Modeling Using an Iterative LS-SVM Method. VLSI-SoC 2009: 118-134 - [e1]Lars Svensson, José Monteiro:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Lecture Notes in Computer Science 5349, Springer 2009, ISBN 978-3-540-95947-2 [contents] - 2008
- [j11]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1013-1026 (2008) - [c37]Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luís Miguel Silveira:
Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS 2008: 247-257 - 2007
- [j10]Eduardo A. C. da Costa, José Monteiro, Sergio Bampi:
A new array architecture for signed multiplication using Gray encoded radix-2m operands. Integr. 40(2): 118-132 (2007) - [c36]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423 - [c35]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Minimum number of operations under a general number representation for digital filter synthesis. ECCTD 2007: 252-255 - [c34]Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS 2007: 424-429 - 2006
- [c33]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674 - [c32]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. ICECS 2006: 748-751 - [c31]Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI 2006: 161-166 - 2005
- [c30]Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Maximal sharing of partial terms in MCM under minimal signed digit representation. ECCTD 2005: 221-224 - [c29]Paulo F. Flores, José Monteiro, Eduardo A. C. da Costa:
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD 2005: 13-16 - [c28]Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro:
Design of a radix-2m hybrid array multiplier using carry save adder format. SBCCI 2005: 172-177 - [c27]Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis:
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC 2005: 25-39 - 2004
- [j9]José C. Costa, Luís Miguel Silveira, Srinivas Devadas, José Monteiro:
Power Estimation Using Probability Polynomials. Des. Autom. Embed. Syst. 9(1): 19-52 (2004) - [c26]Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
An improved synthesis method for low power hardwired FIR filters. SBCCI 2004: 237-241 - 2003
- [c25]Eduardo A. C. da Costa, Sergio Bampi, José Monteiro:
A New Pipelined Array Architecture for Signed Multiplication. SBCCI 2003: 65-70 - [c24]Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. VLSI-SoC (Selected Papers) 2003: 281-297 - [c23]Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. VLSI-SOC 2003: 307- - 2002
- [j8]José C. Monteiro, Arlindo L. Oliveira:
Implicit FSM decomposition applied to low-power design. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 560-565 (2002) - [c22]Eduardo A. C. da Costa, Sergio Bampi, José Monteiro:
A New Architecture for Signed Radix-2m Pure Array Multipliers. ICCD 2002: 112-117 - [c21]Eduardo Costa, Sergio Bampi, José Monteiro:
A New Architecture for 2's Complement Gray Encoded Array Multiplier. SBCCI 2002: 14-19 - 2001
- [c20]Eduardo Costa, Sergio Bampi, José Monteiro:
Power Efficient Arithmetic Operand Encoding. SBCCI 2001: 201-206 - [c19]João Portela, José Monteiro:
Power Optimized Viterbi Decoder Implementation through Architectural Transforms. SBCCI 2001: 212-219 - 2000
- [c18]José C. Monteiro, Arlindo L. Oliveira:
FSM decomposition by direct circuit manipulation applied to low power design. ASP-DAC 2000: 351-358 - [c17]José C. Costa, Srinivas Devadas, José Monteiro:
Observability Analysis of Embedded Software for Coverage-Directed Validation. ICCAD 2000: 27-32 - [c16]Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro:
Probabilistic Bottom-Up RTL Power Estimation. ISQED 2000: 439-
1990 – 1999
- 1999
- [c15]José C. Costa, José Monteiro, L. Miguel Silveira, Srinivas Devadas:
A probabilistic approach for RT-level power modeling. ICECS 1999: 911-914 - [c14]Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José Monteiro:
Integrating Dynamic Power Management in the Design Flow. VLSI 1999: 233-244 - [c13]Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41 - [c12]Srinivas Devadas, Sharad Malik, José Monteiro, Luciano Lavagno:
CAD Techniques for Embedded System Design. VLSI Design 1999: 608 - 1998
- [j7]José Monteiro, Srinivas Devadas:
Power Estimation Under User-Specified Input Sequences and Programs. Integr. Comput. Aided Eng. 5(2): 177-185 (1998) - [j6]José Monteiro, Srinivas Devadas, Abhijit Ghosh:
Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 279-284 (1998) - [c11]José C. Monteiro, Arlindo L. Oliveira:
Finite State Machine Decomposition For Low Power. DAC 1998: 758-763 - [c10]José C. Monteiro:
Techniques for power management at the logic level. ICECS 1998: 181-184 - [c9]José Rufino, Nuno Pedrosa, José Monteiro, Paulo Veríssimo, Guilherme Arroz:
Hardware support for CAN fault-tolerant communication. ICECS 1998: 263-266 - 1997
- [j5]José Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White:
Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 121-127 (1997) - [c8]José C. Costa, José C. Monteiro, Srinivas Devadas:
Switching activity estimation using limited depth reconvergent path analysis. ISLPED 1997: 184-189 - 1996
- [b1]José Carlos Alves Pereira Monteiro:
A computer-aided design methodology for low power circuits. Massachusetts Institute of Technology, Cambridge, MA, USA, 1996 - [j4]Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. 4(4): 495 (1996) - [j3]José Monteiro, Srinivas Devadas:
Techniques for power estimation and optimization at the logic level: A survey. J. VLSI Signal Process. 13(2-3): 259-276 (1996) - [c7]José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar:
Scheduling Techniques to Enable Power Management. DAC 1996: 349-352 - 1995
- [j2]Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 404-416 (1995) - [c6]José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh:
Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444 - [c5]José Monteiro, Srinivas Devadas:
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. ISLPD 1995: 33-38 - 1994
- [j1]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 426-436 (1994) - [c4]José Monteiro, Srinivas Devadas, Bill Lin:
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. DAC 1994: 12-17 - [c3]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81 - [c2]José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto:
Bitwise Encoding of Finite State Machines. VLSI Design 1994: 379-382 - 1993
- [c1]José Monteiro, Srinivas Devadas, Abhijit Ghosh:
Retiming sequential circuits for low power. ICCAD 1993: 398-402
Coauthor Index
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