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2010 – 2019
- 2019
[j44]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019)- 2017
- [j43]Magdy S. Abadir, Jayanta Bhadra, Wen Chen, Li-C. Wang:
Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. IEEE Des. Test 34(5): 5-6 (2017) - [j42]Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang:
Challenges and Trends in Modern SoC Design Verification. IEEE Des. Test 34(5): 7-22 (2017) - 2014
- [c106]Li-C. Wang, Magdy S. Abadir:
Data Mining In EDA - Basic Principles, Promises, and Constraints. DAC 2014: 159:1-159:6 - [c105]Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
Multivariate outlier modeling for capturing customer returns - How simple it can be. IOLTS 2014: 164-169 - [c104]Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
Yield optimization using advanced statistical correlation methods. ITC 2014: 1-10 - 2013
- [j41]Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C. Wang:
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. J. Electron. Test. 29(5): 621-623 (2013) - [c103]Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir:
Simulation knowledge extraction and reuse in constrained random processor verification. DAC 2013: 120:1-120:6 - [c102]Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
A pattern mining framework for inter-wafer abnormality analysis. ITC 2013: 1-10 - [c101]Sani R. Nassif, Yale N. Patt, Magdy S. Abadir:
Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC 2013 - [c100]Wen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir:
Novel test analysis to improve structural coverage - A commercial experiment. VLSI-DAT 2013: 1-4 - 2012
- [j40]Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta:
Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. 17(3): 19:1-19:3 (2012) - [c99]Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir:
Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD 2012: 101-108 - [c98]Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
Screening customer returns with multivariate test analysis. ITC 2012: 1-10 - [c97]Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
An experiment of burn-in time reduction based on parametric test analysis. ITC 2012: 1-10 - [c96]Magdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang:
Data mining based prediction paradigm and its applications in design automation. VLSI-DAT 2012: 1 - 2011
- [c95]Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir:
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. DATE 2011: 794-799 - [c94]Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
Forward prediction based on wafer sort data - A case study. ITC 2011: 1-10 - [c93]Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
Understanding customer returns from a test perspective. VTS 2011: 2-7 - [e5]Magdy S. Abadir, Jay Bhadra, Li-C. Wang:
12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-2101-4 [contents] - 2010
- [j39]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. IEEE Des. Test Comput. 27(3): 42-53 (2010) - [c92]Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir:
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. DAC 2010: 374-379 - [c91]Alper Sen, Magdy S. Abadir:
Coverage metrics for verification of concurrent SystemC designs using mutation testing. HLDVT 2010: 75-81 - [c90]Magdy S. Abadir:
Design for reality: knowledge discovery in design and test data. SBCCI 2010: 54 - [e4]Magdy S. Abadir, Jay Bhadra, Li-C. Wang:
11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4354-3 [contents]
2000 – 2009
- 2009
- [j38]Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir:
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1728-1741 (2009) - [c89]Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir:
TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE 2009: 340-345 - [c88]Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir:
Minimizing outlier delay test cost in the presence of systematic variability. ITC 2009: 1-10 - 2008
- [j37]Pouria Bastani, Li-C. Wang, Magdy S. Abadir:
Linking Statistical Learning to Diagnosis. IEEE Des. Test Comput. 25(3): 232-239 (2008) - [j36]Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir:
Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 388-396 (2008) - [c87]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Statistical diagnosis of unmodeled systematic timing effects. DAC 2008: 355-360 - [c86]Alper Sen, Vinit Ogale, Magdy S. Abadir:
Predictive runtime verification of multi-processor SoCs in SystemC. DAC 2008: 948-953 - [c85]Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED 2008: 470-475 - [c84]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC 2008: 1-10 - 2007
- [j35]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang:
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Des. Test Comput. 24(2): 110-111 (2007) - [j34]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray:
A Survey of Hybrid Techniques for Functional Verification. IEEE Des. Test Comput. 24(2): 112-122 (2007) - [c83]Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC 2007: 274-279 - [c82]Li-C. Wang, Pouria Bastani, Magdy S. Abadir:
Design-Silicon Timing Correlation A Data Mining Perspective. DAC 2007: 384-389 - [c81]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 - [c80]Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir:
Analyzing the risk of timing modeling based on path delay tests. ITC 2007: 1-10 - [c79]Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Statistical analysis and optimization of parametric delay test. ITC 2007: 1-10 - [c78]Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design 2007: 559-564 - [e3]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra:
Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA. IEEE Computer Society 2007, ISBN 978-0-7695-3241-7 [contents] - 2006
- [c77]Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS 2006: 118-123 - [c76]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Refined statistical static timing analysis through. DAC 2006: 149-154 - [c75]Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir:
Extracting a simplified view of design functionality via vector simulation. HLDVT 2006: 195-202 - [c74]Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir:
Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference 2006: 34-49 - [c73]Magdy S. Abadir:
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. IOLTS 2006: 81 - [c72]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. ITC 2006: 1-10 - [c71]Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir:
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36 - [c70]Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir:
A Trace-Driven Validation Methodology for Multi-Processor SOCS. SoCC 2006: 145-148 - [e2]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra:
Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA. IEEE Computer Society 2006, ISBN 978-0-7695-2839-7 [contents] - 2005
- [j33]Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi:
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electron. Test. 21(5): 495-502 (2005) - [j32]Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir:
A methodology for validation of microprocessors using symbolic simulation. Int. J. Embed. Syst. 1(1/2): 14-22 (2005) - [c69]Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris:
Choosing flows and methodologies for SoC design. DAC 2005: 167 - [c68]Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196 - [c67]Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis:
Establishing latch correspondence for embedded circuits of PowerPC microprocessors. HLDVT 2005: 37-44 - [c66]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876 - [c65]Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir:
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. ITC 2005: 10 - [c64]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47 - [c63]Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova:
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118 - [c62]Brian Kahne, Magdy S. Abadir:
Retiming Verification Using Sequential Equivalence Checking. MTV 2005: 138-142 - [c61]Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea:
Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design 2005: 14 - [c60]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. VTS 2005: 153-160 - [e1]Magdy S. Abadir, Li-C. Wang:
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA. IEEE Computer Society 2005, ISBN 0-7695-2627-6 [contents] - 2004
- [j31]Magdy S. Abadir, Li-C. Wang:
Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. IEEE Des. Test Comput. 21(2): 80-82 (2004) - [j30]Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir:
A Top-Down Methodology for Microprocessor Validation. IEEE Des. Test Comput. 21(2): 122-131 (2004) - [j29]Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir:
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Des. Test Comput. 21(6): 494-502 (2004) - [j28]Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir:
IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1361-1369 (2004) - [c59]Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir:
Analytical models for leakage power estimation of memory array structures. CODES+ISSS 2004: 146-151 - [c58]Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir:
On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497 - [c57]Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209 - [c56]Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri:
Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) 2004: 221-224 - [c55]Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37 - [c54]Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49 - [c53]M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu:
Identification of Gates for Covering all Critical Paths. MTV 2004: 92-96 - [c52]Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109 - [c51]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115- - 2003
- [j27]Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey:
Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Des. Autom. Embed. Syst. 8(2-3): 173-188 (2003) - [j26]Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin:
Formal Verification Successes at Motorola. Formal Methods Syst. Des. 22(2): 117-123 (2003) - [c50]Andreas G. Veneris, Alexander Smith, Magdy S. Abadir:
Logic verification based on diagnosis techniques. ASP-DAC 2003: 93-98 - [c49]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir:
Enhanced symbolic simulation for efficient verification of embedded array systems. ASP-DAC 2003: 302-307 - [c48]Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir:
An automated method for test model generation from switch level circuits. ASP-DAC 2003: 769-774 - [c47]Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu:
Automated Test Model Generation from Switch Level Custom Circuits. Asian Test Symposium 2003: 184-189 - [c46]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE 2003: 10328-10335 - [c45]Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir:
IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD 2003: 113-119 - [c44]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050 - [c43]Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir:
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37 - [c42]Magdy S. Abadir, Juhong Zhu:
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. VTS 2003: 22-30 - 2002
- [j25]Andreas G. Veneris, Magdy S. Abadir:
Design rewiring using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1469-1479 (2002) - [c41]Jing Zeng, Magdy S. Abadir, Jacob A. Abraham:
False timing path identification using ATPG techniques and delay-based information. DAC 2002: 562-565 - [c40]Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir:
Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE 2002: 716-721 - [c39]Ad J. van de Goor, Magdy S. Abadir, Alan Carlin:
Minimal Test for Coupling Faults in Word-Oriented Memories. DATE 2002: 944-948 - [c38]Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212 - [c37]Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri:
Design Rewiring Using ATPG. ITC 2002: 223-232 - [c36]Li-C. Wang, Magdy S. Abadir, Juhong Zhu:
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. ITC 2002: 398-406 - [c35]Li-C. Wang, Magdy S. Abadir:
Validation and Verification of Complex Digital Systems: A Practical Perspective. LATW 2002: 1 - [c34]Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir:
Efficient and Exact Diagnosis of Multiple Stuck-At Faults. LATW 2002: 132-136 - [c33]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280 - 2001
- [j24]Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham:
Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Des. Test Comput. 18(4): 26-35 (2001) - [j23]Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir:
Very Low Cost Testers: Opportunities and Challenges. IEEE Des. Test Comput. 18(5): 60-69 (2001) - [c32]Andreas G. Veneris, Magdy S. Abadir, Ivor Ting:
Design rewiring based on diagnosis techniques. ASP-DAC 2001: 479-484 - [c31]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir:
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402 - [c30]Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham:
Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519 - [c29]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir:
A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. HLDVT 2001: 134-141 - [c28]Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir:
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65- - [c27]Magdy S. Abadir, Li-C. Wang:
Verification and Validation of Complex Digital Systems: An Industrial Perspective. ISQED 2001: 11-12 - [c26]Ivor Ting, Andreas G. Veneris, Magdy S. Abadir:
ATPG Driven Logic Synthesis for Delay and Power Minimization. LATW 2001: 96-99 - [c25]Magdy S. Abadir, Juhong Zhu, Li-C. Wang:
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. VTS 2001: 252-259 - [c24]Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma:
ATPG for Design Errors-Is It Possible? VTS 2001: 283-285 - 2000
- [j22]Magdy S. Abadir, Sumit Dasgupta:
Guest Editors' Introduction: Microprocessor Test and Verification. IEEE Des. Test Comput. 17(4): 4-5 (2000) - [j21]Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham:
Validating PowerPC Microprocessor Custom Memories. IEEE Des. Test Comput. 17(4): 61-76 (2000) - [j20]Magdy S. Abadir:
Guest Editorial. J. Electron. Test. 16(1-2): 9-10 (2000) - [j19]Li-C. Wang, Magdy S. Abadir:
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. J. Electron. Test. 16(1-2): 121-130 (2000) - [j18]Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. 16(1-2): 147-155 (2000) - [c23]Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor. CICC 2000: 71-74 - [c22]Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham:
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor. LATW 2000: 72-76 - [c21]Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji:
Design Optimization Based on Diagnosis Techniques. LATW 2000: 244-249 - [c20]Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham:
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14
1990 – 1999
- 1999
- [j17]Li-C. Wang, Magdy S. Abadir:
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. J. Electron. Test. 15(1-2): 191-205 (1999) - [c19]Magdy S. Abadir, Rajesh Raina:
Design-for-test methodology for Motorola PowerPC microprocessors. ITC 1999: 810-819 - [c18]Li-C. Wang, Magdy S. Abadir:
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. ITC 1999: 830-838 - 1998
- [j16]Li-C. Wang, Magdy S. Abadir:
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. J. Electron. Test. 13(2): 121-135 (1998) - [j15]Li-C. Wang, Magdy S. Abadir, Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998) - [c17]Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy:
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. DAC 1998: 534-537 - [c16]Li-C. Wang, Magdy S. Abadir, Jing Zeng:
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. DATE 1998: 273-277 - [c15]Arun Chandra, Li-C. Wang, Magdy S. Abadir:
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. Great Lakes Symposium on VLSI 1998: 362-367 - [c14]Li-C. Wang, Magdy S. Abadir, Jing Zeng:
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. VTS 1998: 260-265 - 1997
- [j14]Tony Ambler, Magdy S. Abadir:
Design and Test Economics-An Extra Dimension. IEEE Des. Test Comput. 14(3): 15-16 (1997) - [j13]Magdy S. Abadir, Rohit Kapur:
Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Des. Test Comput. 14(3): 45-50 (1997) - [j12]Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn:
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. J. Electron. Test. 10(1-2): 151-166 (1997) - [j11]Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997) - [c13]Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir:
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. DAC 1997: 167-172 - [c12]Li-C. Wang, Magdy S. Abadir:
A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. ITC 1997: 954-963 - [c11]Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther:
Microprocessor Test and Validation: Any New Avenues? VTS 1997: 458-464 - 1996
- [c10]Neeta Ganguly, Magdy S. Abadir, Manish Pandey:
PowerPCTM Array Verification Methodology using Formal Techniques. ITC 1996: 857-864 - 1994
- [j10]Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake:
Analyzing Multichip Module Testing Strategies. IEEE Des. Test Comput. 11(1): 40-52 (1994) - [j9]Magdy S. Abadir, Tony Ambler:
Introduction. J. Electron. Test. 5(2-3): 129-130 (1994) - [j8]Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy:
High Level Test Economics Advisor (Hi-TEA). J. Electron. Test. 5(2-3): 195-206 (1994) - [j7]Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh:
Multichip systems trade-off analysis tool. J. Electron. Test. 5(2-3): 207-218 (1994) - [c9]James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275 - 1993
- [c8]Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir:
AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD 1993: 63-66 - 1992
- [c7]Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir:
Automatic Test Knowledge Extraction from VHDL (ATKET). DAC 1992: 273-278 - 1991
- [c6]Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer:
Partitioning Hierarchical Designs for Testability. ITC 1991: 174-183 - 1990
- [c5]Magdy S. Abadir, Jack Ferguson:
An improved layout verification algorithm (LAVA). EURO-DAC 1990: 391-395
1980 – 1989
- 1989
- [c4]Magdy S. Abadir:
TIGER: testability insertion guidance expert system. ICCAD 1989: 562-565 - 1988
- [j6]Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland:
Logic design verification via test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 138-148 (1988) - 1986
- [j5]Magdy S. Abadir, Melvin A. Breuer:
Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers 35(4): 361-367 (1986) - [j4]Magdy S. Abadir, Hassan K. Reghbati:
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. IEEE Trans. Computers 35(4): 375-379 (1986) - [c3]Magdy S. Abadir, Melvin A. Breuer:
Scan Path with Look Ahead Shifting (SPLASH). ITC 1986: 696-704 - 1985
- [j3]Magdy S. Abadir, Melvin A. Breuer:
A Knowledge-Based System for Designing Testable VLSI Chips. IEEE Des. Test 2(4): 56-68 (1985) - [c2]Magdy S. Abadir, Hassan K. Reghbati:
Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. ITC 1985: 483-492 - 1984
- [c1]Magdy S. Abadir, Hassan K. Reghbati:
Test generation for LSI: A case study. DAC 1984: 180-195 - 1983
- [j2]Magdy S. Abadir, Hassan K. Reghbati:
Functional Testing of Semiconductor Random Access Memories. ACM Comput. Surv. 15(3): 175-198 (1983) - [j1]Magdy S. Abadir, Hassan K. Reghbati:
LSI Testing Techniques. IEEE Micro 3(1): 34-51 (1983)
Coauthor Index
Jayanta Bhadra
aka: Jay Bhadra
aka: Jay Bhadra
[j43] [j42] [c106] [c105] [c104] [j41] [c103] [c102] [c100] [j40] [c99] [c98] [c97] [c96] [c95] [c94] [c93] [e5] [j39] [c92] [e4] [j38] [c88] [j37] [c87] [c84] [j35] [j34] [c82] [c80] [c79] [e3] [c76] [c75] [c74] [c72] [e2] [c65] [c60] [e1] [j31] [c58] [c55] [c52] [j27] [c49] [c46] [c44] [c38] [c36] [c35] [c27] [c25] [j19] [j17] [c18] [j16] [j15] [c17] [c16] [c15] [c14] [c12]
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