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ORCIDSorin Cotofana
Sorin Dan Cotofana
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- affiliation: Delft University of Technology, Netherlands
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2020 – today
- 2025
[j38]Fanfan Meng
, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru:
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. IEEE Trans. Circuits Syst. I Regul. Pap. 72(1): 135-142 (2025)- 2024
- [j37]Abdulqader Nael Mahmoud, Florin Ciubotaru, Frederic Vanderveken, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
Two Cascaded Spin Wave Majority Gates Operation Under Continuous and Pulse Modes. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1919-1923 (2024) - [j36]Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao:
CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. IEEE Trans. Emerg. Top. Comput. 12(4): 980-990 (2024) - [j35]Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao:
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. IEEE Trans. Neural Networks Learn. Syst. 35(9): 12913-12923 (2024) - [c129]Nicoleta Cucu Laurencin, Charles Timmermans, Sorin Dan Cotofana:
An Energy-Efficient Graphene-based Spiking Neural Network Architecture for Pattern Recognition. ISCAS 2024: 1-5 - [i8]Christoph Adelmann, Florin Ciubotaru, Fanfan Meng, Sorin Cotofana, Sebastien Couet:
Spintronic logic: from transducers to logic gates and circuits. CoRR abs/2401.10007 (2024) - [i7]Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana:
Spin Wave Threshold Gate. CoRR abs/2401.12136 (2024) - 2023
- [c128]Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana:
Spin Wave Threshold Logic Gates. NANOARCH 2023: 31:1-31:6 - [i6]Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Kang Wang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto:
Roadmap for Unconventional Computing with Nanotechnology. CoRR abs/2301.06727 (2023) - 2022
- [j34]Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana:
Non-Binary Spin Wave Based Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3888-3900 (2022) - [j33]Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana:
Spin Wave Based Approximate Computing. IEEE Trans. Emerg. Top. Comput. 10(4): 1932-1940 (2022) - [c127]Abdulqader Nael Mahmoud, Nicoleta Cucu Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
Would Magnonic Circuits Outperform CMOS Counterparts? ACM Great Lakes Symposium on VLSI 2022: 309-313 - 2021
- [j32]He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Cotofana:
Graphene-Based Artificial Synapses with Tunable Plasticity. ACM J. Emerg. Technol. Comput. Syst. 17(4): 50:1-50:21 (2021) - [j31]Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui:
Spin Wave Normalization Toward All Magnonic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 536-549 (2021) - [j30]Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao:
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. 32(4): 1703-1712 (2021) - [c126]Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui:
Fan-out of 2 Triangle Shape Spin Wave Logic Gates. DATE 2021: 948-953 - [c125]Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
Spin Wave Based 4-2 Compressor. ICECS 2021: 1-4 - [c124]Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
Spin Wave Based Full Adder. ISCAS 2021: 1-5 - [c123]Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana:
Achieving Wave Pipelining in Spin Wave Technology. ISQED 2021: 54-59 - 2020
- [j29]Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang:
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. 67-I(12): 4247-4258 (2020) - [j28]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Reliability Aware Design and Lifetime Management of Computing Platforms. IEEE Trans. Emerg. Top. Comput. 8(3): 602-615 (2020) - [c122]Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
n-bit Data Parallel Spin Wave Logic Gate. DATE 2020: 642-645 - [c121]Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott:
Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA. GECCO 2020: 1125-1133 - [c120]Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana:
4-output Programmable Spin Wave Logic Gate. ICCD 2020: 332-335 - [c119]Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott:
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. FPT 2020: 48-55 - [c118]Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis:
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. ISCAS 2020: 1-5 - [c117]He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana:
Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron. ISCAS 2020: 1-5 - [c116]Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui:
2-Output Spin Wave Programmable Logic Gate. ISVLSI 2020: 60-65 - [i5]Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis:
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case. CoRR abs/2002.06339 (2020) - [i4]Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott:
Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA. CoRR abs/2003.12449 (2020) - [i3]Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao:
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR abs/2005.03857 (2020) - [i2]Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott:
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. CoRR abs/2011.07317 (2020)
2010 – 2019
- 2019
- [j27]Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
On Basic Boolean Function Graphene Nanoribbon Conductance Mapping. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1948-1959 (2019) - [c115]Vasileios G. Ntinas, Antonio Rubio, Georgios Ch. Sirakoulis, Sorin Dan Cotofana:
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement. ISCAS 2019: 1-5 - [c114]He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana:
Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model. ISCAS 2019: 1-5 - [c113]He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana:
Graphene Nanoribbon-based Synapses with Versatile Plasticity. NANOARCH 2019: 1-6 - 2018
- [j26]Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana:
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. IEEE Trans. Emerg. Top. Comput. 6(2): 184-199 (2018) - [c112]Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps. ISCAS 2018: 1-5 - [c111]Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Cotofana:
Complementary Arranged Graphene Nanoribbon-based Boolean Gates. NANOARCH 2018: 51-57 - 2017
- [j25]Changlin Chen, Yaowen Fu, Sorin Cotofana:
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 285-298 (2017) - [j24]George Razvan Voicu, Sorin Dan Cotofana:
High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders. IEEE Trans. Emerg. Top. Comput. 5(2): 179-192 (2017) - [c110]Xu He, Yao Wang, Yang Guo, Sorin Cotofana:
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. ACM Great Lakes Symposium on VLSI 2017: 29-34 - [c109]Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana:
LDPC-Based Adaptive Multi-Error Correction for 3D Memories. ICCD 2017: 265-268 - [c108]Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana:
Low cost multi-error correction for 3D polyhedral memories. NANOARCH 2017: 13-18 - [c107]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Fast and accurate workload-level neural network based IC energy consumption estimation. SMACD 2017: 1-4 - [c106]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Haar-based interconnect coding for energy effective medium/long range data transport. SoCC 2017: 375-380 - 2016
- [j23]Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota:
Brownian Circuits: Designs. Int. J. Unconv. Comput. 12(5-6): 341-362 (2016) - [c105]Thien Truong Nguyen-Ly, Tushar Gupta, Manuel Pezzin, Valentin Savin, David Declercq, Sorin Cotofana:
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units. DSD 2016: 230-237 - [c104]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel:
TFET NDR skewed inverter based sensing method. NANOARCH 2016: 13-14 - [c103]Nicoleta Cucu Laurenciu, Tushar Gupta, Valentin Savin, Sorin Dan Cotofana:
Error Correction Code protected Data Processing Units. NANOARCH 2016: 37-42 - [c102]Bo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana:
A supply voltage-dependent variation aware reliability evaluation model. NANOARCH 2016: 79-84 - 2015
- [j22]Jiaoyan Chen, Sorin Cotofana, Satish Grandhi, Christian Spagnol, Emanuel M. Popovici:
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits. Microelectron. Reliab. 55(12): 2754-2761 (2015) - [c101]Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana:
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. ASYNC 2015: 132-138 - [c100]Changlin Chen, Marius Enachescu, Sorin Dan Cotofana:
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems. DATE 2015: 507-512 - [c99]Alexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana:
Hybrid adaptive clock management for FPGA processor acceleration. DATE 2015: 1359-1364 - [c98]Thomas Marconi, Sorin Cotofana:
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. ACM Great Lakes Symposium on VLSI 2015: 245-248 - [c97]Satish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits. ICCD 2015: 431-434 - [c96]Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana:
A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. ISCAS 2015: 425-428 - [c95]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Low cost and energy, thermal noise driven, probability modulated random number generator. ISCAS 2015: 2724-2727 - 2014
- [j21]Héctor Pettenghi, Sorin Cotofana, Leonel Sousa:
Efficient Method for Designing Modulo {2n ± k} Multipliers. J. Circuits Syst. Comput. 23(1) (2014) - [j20]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Critical transistors nexus based circuit-level aging assessment and prediction. J. Parallel Distributed Comput. 74(6): 2512-2520 (2014) - [j19]Yao Wang, Sorin Dan Cotofana, Liang Fang:
Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. J. Parallel Distributed Comput. 74(6): 2521-2529 (2014) - [c94]Hillary Siewobr, Kazeem Alagbe Gbolagade, Sorin Cotofana:
An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1, 2n + 1}. ISIC 2014: 508-511 - [c93]Jiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana, Alexandru Amaricai:
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. ISVLSI 2014: 380-385 - [c92]Changlin Chen, Sorin Dan Cotofana:
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs. ISVLSI 2014: 492-497 - [c91]Changlin Chen, Sorin Cotofana:
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs. NoCArc@MICRO 2014: 5-10 - [c90]Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana:
Energy effective 3D stacked hybrid NEMFET-CMOS caches. NANOARCH 2014: 151-156 - [c89]Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana:
Robust sub-powered asynchronous logic. PATMOS 2014: 1-7 - [c88]Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
Towards energy effective LDPC decoding by exploiting channel noise variability. VLSI-SoC 2014: 1-6 - [c87]Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
Transmission Channel Noise Aware Energy Effective LDPC Decoding. VLSI-SoC (Selected Papers) 2014: 198-219 - [e1]Jacques-Olivier Klein, Csaba Andras Moritz, Sorin Cotofana:
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014. IEEE Computer Society/ACM 2014, ISBN 978-1-4799-6383-6 [contents] - 2013
- [j18]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
A nonlinear degradation path dependent end-of-life estimation framework from noisy observations. Microelectron. Reliab. 53(9-11): 1213-1217 (2013) - [c86]George Razvan Voicu, Mihai Lefter, Marius Enachescu, Sorin Dan Cotofana:
3D stacked wide-operand adders: A case study. ASAP 2013: 133-141 - [c85]Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade, Sorin Dan Cotofana:
An effective New CRT based reverse converter for a novel moduli set {22n+1 - 1, 22n+1, 22n - 1}. ASAP 2013: 142-146 - [c84]Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana:
Is TSV-based 3D integration suitable for inter-die memory repair? DATE 2013: 1251-1254 - [c83]Changlin Chen, Sorin Dan Cotofana:
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs. DSD 2013: 311-318 - [c82]Yao Wang, Sorin Dan Cotofana, Liang Fang:
Lifetime reliability assessment with aging information from low-level sensors. ACM Great Lakes Symposium on VLSI 2013: 339-340 - [c81]Marius Enachescu, Mihai Lefter, Antonios Bazigos, Adrian M. Ionescu, Sorin Dan Cotofana:
Ultra low power NEMFET based logic. ISCAS 2013: 566-569 - [c80]George Razvan Voicu, Sorin Dan Cotofana:
Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing. NANOARCH 2013: 122-127 - [c79]Changlin Chen, Sorin Dan Cotofana:
A low cost method to tolerate soft errors in the NoC router control plane. SoCC 2013: 374-379 - [c78]Nicoleta Cucu Laurenciu, Yao Wang, Sorin Dan Cotofana:
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. VLSI-SoC 2013: 246-251 - 2012
- [j17]Yao Wang, Marius Enachescu, Sorin Dan Cotofana, Liang Fang:
Variation tolerant on-chip degradation sensors for dynamic reliability management systems. Microelectron. Reliab. 52(9-10): 1787-1791 (2012) - [j16]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Context aware slope based transistor-level aging model. Microelectron. Reliab. 52(9-10): 1792-1796 (2012) - [c77]Andrew Nelson, Anca Molnos, Ashkan Beyranvand Nejad, Davit Mirzoyan, Sorin Cotofana, Kees Goossens:
Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints. WESE 2012: 7 - [c76]George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana:
A 3D stacked high performance scalable architecture for 3D Fourier Transform. ICCD 2012: 498-499 - [c75]Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana:
Is the road towards "Zero-Energy" paved with NEMFET-based power management? ISCAS 2012: 2561-2564 - [c74]Yao Wang, Sorin Dan Cotofana, Liang Fang:
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. NANOARCH 2012: 109-115 - [c73]Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
A Markovian, variation-aware circuit-level aging model. NANOARCH 2012: 116-122 - [c72]Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana:
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. NANOARCH 2012: 123-130 - [c71]Saleh Safiruddin, Sorin Cotofana, Ferdinand Peper:
Stigmergic search with single electron tunneling technology based memory enhanced hubs. NANOARCH 2012: 174-180 - [c70]Changlin Chen, Ye Lu, Sorin Dan Cotofana:
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip. NOCS 2012: 124-131 - [c69]Anca Mariana Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana, Kees Goossens:
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms. Map2MPSoC/SCOPES 2012: 13-21 - 2011
- [j15]Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana:
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1500-1503 (2011) - [c68]Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink:
Composable local memory organisation for streaming applications on embedded MPSoCs. Conf. Computing Frontiers 2011: 23 - [c67]Dennis Andrade, Antonio Rubio, Antonio Calomarde, Sorin Dan Cotofana:
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations. ISCAS 2011: 2585-2588 - [c66]Yao Wang, Sorin Cotofana, Liang Fang:
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits. NANOARCH 2011: 175-180 - [c65]George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana:
Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs. NANOARCH 2011: 203-209 - [c64]Demid Borodin, Winston Siauw, Sorin Dan Cotofana:
Functional unit sharing between stacked processors in 3D integrated systems. ICSAMOS 2011: 311-317 - 2010
- [c63]Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana:
Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set. ASAP 2010: 301-304 - [c62]Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana:
A unified addition structure for moduli set {2n-1, 2n, 2n+1} based on a novel RNS representation. ICCD 2010: 247-252 - [c61]Kazeem Alagbe Gbolagade, Ricardo Chaves, Leonel Sousa, Sorin Dan Cotofana:
An improved RNS reverse converter for the {22n+1-1, 2n, 2n-1} moduli set. ISCAS 2010: 2103-2106
2000 – 2009
- 2009
- [j14]Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven:
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors. J. Signal Process. Syst. 57(2): 155-172 (2009) - [c60]Kazeem Alagbe Gbolagade, Sorin Dan Cotofana:
A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}. ICECS 2009: 113-116 - [c59]Kazeem Alagbe Gbolagade, Sorin Cotofana:
An O(n) Residue Number System to Mixed Radix Conversion Technique. ISCAS 2009: 521-524 - [c58]Ben Kuiper, Sorin Cotofana:
Adaptive Clock Scheduling for pipelined structures. NANOARCH 2009: 65-68 - [c57]Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu:
Can SG-FET Replace FET in Sleep Mode Circuits? NanoNet 2009: 99-104 - [c56]Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana:
Emerging non-CMOS nanoelectronic devices - What are they?. NEMS 2009: 63-68 - 2008
- [j13]Ben H. H. Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis:
GRAAL: A Framework for Low-Power 3D Graphics Accelerators. IEEE Computer Graphics and Applications 28(4): 63-73 (2008) - [c55]Kazeem Alagbe Gbolagade, Sorin Dan Cotofana:
A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set. ACSCC 2008: 1785-1789 - [c54]Kazeem Alagbe Gbolagade, Sorin Dan Cotofana:
Generalized matrix method for efficient residue to decimal conversion. APCCAS 2008: 1414-1417 - [c53]Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana:
Compositional, dynamic cache management for embedded chip multiprocessors. DATE 2008: 991-996 - [c52]Radu Andrei Stefan, Sorin Dan Cotofana:
Bitstream compression techniques for Virtex 4 FPGAs. FPL 2008: 323-328 - [c51]Saleh Safiruddin, Sorin Dan Cotofana, Ferdinand Peper:
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits. NANOARCH 2008: 69-76 - 2007
- [j12]Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven:
Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors. Trans. High Perform. Embed. Archit. Compil. 1: 279-297 (2007) - [i1]Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven:
Compositional Memory Systems for Multimedia Communicating Tasks. CoRR abs/0710.4658 (2007) - 2006
- [c50]Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven:
Static cache partitioning robustness analysis for embedded on-chip multi-processors. Conf. Computing Frontiers 2006: 353-360 - [c49]Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven:
Compositional, efficient caches for a chip multi-processor. DATE 2006: 345-350 - [c48]Tudor Niculiu, Cristian Lupu, Sorin Cotofana:
Consciousness for modeling intelligence - simulating the evolution by closure to the inverse. ICINCO-ICSO 2006: 187-190 - [c47]Cor Meenderinck, Sorin Cotofana:
Electron counting based high-radix multiplication in single electron tunneling technology. ISCAS 2006 - [c46]Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven:
Throughput optimization via cache partitioning for embedded multiprocessors. ICSAMOS 2006: 185-192 - [c45]Cor Meenderinck, Sorin Cotofana:
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology. SAMOS 2006: 447-456 - 2005
- [j11]Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis:
Addition Related Arithmetic Operations via Controlled Transport of Charge. IEEE Trans. Computers 54(3): 243-256 (2005) - [j10]Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers:
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. J. VLSI Signal Process. 39(3): 195-212 (2005) - [c44]Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267 - [c43]Cor Meenderinck, Sorin Cotofana, Casper Lageweg:
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. ASAP 2005: 294-302 - [c42]Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven:
Compositional Memory Systems for Multimedia Communicating Tasks. DATE 2005: 932-937 - 2004
- [j9]Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang:
Single-electron tunneling transistor implementation of periodic symmetric functions. IEEE Trans. Circuits Syst. II Express Briefs 51-II(11): 593-597 (2004) - [j8]Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
Pel reconstruction on FPGA-augmented TriMedia. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 622-635 (2004) - [j7]Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang, Qiyu Cai:
Analog-to-digital converter based on single-electron tunneling transistors. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1209-1213 (2004) - [c41]Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
Binary Multiplication based on Single Electron Tunneling. ASAP 2004: 152-166 - [c40]Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha:
Efficient Hardware for Antialiasing Coverage Mask Generation. Computer Graphics International 2004: 257-264 - [c39]Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven:
Compositional Memory Systems for Data Intensive Applications. DATE 2004: 728-729 - [c38]Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha:
GRAAL - A Development Framework for Embedded Graphics Accelerators. DATE 2004: 1366-1367 - [c37]Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang:
Analysis of analog to digital converter based on single-electron tunnelling transistors. ISCAS (3) 2004: 693-696 - [c36]Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha:
Low cost and latency embedded 3D graphics reciprocation. ISCAS (2) 2004: 905-908 - [c35]Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis:
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI 2004: 127-134 - [c34]Peter Celinski, Derek Abbott, Sorin Cotofana:
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. PATMOS 2004: 899-906 - [c33]Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha:
High-Level Energy Estimation for ARM-Based SOCs. SAMOS 2004: 168-177 - 2003
- [j6]Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana:
Microcode Processing: Positioning and Directions. IEEE Micro 23(4): 21-31 (2003) - [c32]Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis:
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. IEEE Symposium on Computer Arithmetic 2003: 245-252 - [c31]Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven:
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. ASAP 2003: 250-259 - [c30]Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana:
A Hierarchical Sparse Matrix Storage Format for Vector Processors. IPDPS 2003: 61 - [c29]Peter Celinski, Derek Abbott, Sorin Dan Cotofana:
Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ISCAS (5) 2003: 233-236 - [c28]Marius Padure, Sorin Cotofana, Stamatis Vassiliadis:
Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. ISCAS (5) 2003: 253-256 - [c27]Marius Padure, Sorin Cotofana, Stamatis Vassiliadis:
CMOS Implementation of Generalized Threshold Functions. IWANN (2) 2003: 65-72 - [c26]Peter Celinski, Sorin Cotofana, Derek Abbott:
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. IWANN (2) 2003: 73-80 - [c25]Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana:
D-SAB: A Sparse Matrix Benchmark Suite. PaCT 2003: 549-554 - [c24]Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. VLSI-SoC (Selected Papers) 2003: 247-262 - [c23]Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. VLSI-SOC 2003: 258-262 - 2002
- [c22]Tudor Niculiu, Sorin Cotofana:
Hierarchical Intellignet Mixed Simulation. ESM 2002: 159-162 - [c21]Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana:
A Sum of Absolute Differences Implementation in FPGA Hardware. EUROMICRO 2002: 183-188 - [c20]Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. FCCM 2002: 261- - [c19]Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers:
Field-Programmable Custom Computing Machines - A Taxonomy -. FPL 2002: 79-88 - [c18]Stephan Wong, Bastiaan Stougie, Sorin Cotofana:
Alternatives in FPGA-based SAD implementations. FPT 2002: 449-452 - [c17]Marius Padure, Sorin Cotofana, Stamatis Vassiliadis, Claudius Dan, Mircea Bodea:
A low-power threshold logic family. ICECS 2002: 657-660 - [c16]Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
A full adder implementation using SET based linear threshold gates. ICECS 2002: 665-668 - [c15]Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana:
Microcoded Reconfigurable Embedded Processors: Current Developments. Embedded Processor Design Challenges 2002: 207-223 - [c14]Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. Embedded Processor Design Challenges 2002: 224-241 - 2001
- [c13]Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana:
Topic 15+20: Multimedia and Embedded Systems. Euro-Par 2001: 651-652 - [c12]Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers:
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. FCCM 2001: 160-169 - [c11]Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana:
The MOLEN rho-mu-Coded Processor. FPL 2001: 275-285 - [c10]Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. ICCD 2001: 425-430 - [c9]Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis:
Coarse Reconfigurable Multimedia Unit Extension. PDP 2001: 235-242 - 2000
- [j5]Sorin Cotofana, Stamatis Vassiliadis:
Signed Digit Addition and Related Operations with Threshold Logic. IEEE Trans. Computers 49(3): 193-207 (2000) - [c8]Tudor Niculiu, Chouki Aktouf, Sorin Cotofana:
Hierarchical interfaces for hardware software systems. ESM 2000: 647-654 - [c7]Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis:
Counter Based Superscalar Instruction Issuing. EUROMICRO 2000: 1307-1315 - [c6]Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal:
Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). Euro-Par 2000: 965-968 - [c5]Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis:
Multimedia Enhanced General-Purpose Processors. IEEE International Conference on Multimedia and Expo (III) 2000: 1493-1496 - [c4]Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis:
General-Purpose Processor Huffman Encoding Extension. ITCC 2000: 158-163
1990 – 1999
- 1999
- [j4]Sorin Cotofana, Stamatis Vassiliadis:
Serial binary multiplication with feed-forward neural networks. Neurocomputing 28(1-3): 1-19 (1999) - [c3]Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis:
Vector ISA Extension for Sparse Matrix-Vector Multiplication. Euro-Par 1999: 708-715 - 1998
- [j3]Sorin Cotofana, Stamatis Vassiliadis:
Periodic symmetric functions, serial addition, and multiplication with neural networks. IEEE Trans. Neural Networks 9(6): 1118-1128 (1998) - [c2]Sorin Cotofana, Stamatis Vassiliadis:
On the Design Complexity of the Issue Logic of Superscalar Machines. EUROMICRO 1998: 10277-10284 - 1996
- [j2]Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels:
2-1 Additions and Related Arithmetic Operations with Threshold Logic. IEEE Trans. Computers 45(9): 1062-1067 (1996) - [j1]Sorin Cotofana, Stamatis Vassiliadis:
delta-Bit serial binary addition with linear threshold networks. J. VLSI Signal Process. 14(3): 249-264 (1996) - [c1]Sorin Cotofana, Stamatis Vassiliadis:
Serial Binary Addition with Polynominally Bounded Weights. ICANN 1996: 741-746
Coauthor Index
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