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ORCIDJanusz Rajski
Person information
- affiliation: Siemens Digital Industries Software, Wilsonville, OR, USA
- affiliation (former): Mentor Graphics Corporation, Wilsonville, OR, USA
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Journal Articles
- 2024
[j85]Janusz Rajski
, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
H2B: Crypto Hash Functions Based on Hybrid Ring Generators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 442-455 (2024)- [j84]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 694-703 (2024) - 2023
- [j83]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
A Lightweight True Random Number Generator for Root of Trust Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2815-2825 (2023) - [j82]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4260-4269 (2023) - [j81]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 411-420 (2023) - 2022
- [j80]Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer:
LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2290-2300 (2022) - [j79]Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski:
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2323-2336 (2022) - 2021
- [j78]Friedrich Hapke, Will Howell, Peter C. Maxwell, Edward Brazil, Srikanth Venkataraman, Rudrajit Dutta, Andreas Glowatz, Anja Fast, Janusz Rajski:
Defect-Oriented Test: Effectiveness in High Volume Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 584-597 (2021) - [j77]Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9(2): 680-691 (2021) - [j76]Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 76-88 (2021) - [j75]Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1553-1566 (2021) - 2020
- [j74]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37(4): 21-26 (2020) - [j73]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1699-1710 (2020) - [j72]Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2964-2975 (2020) - 2019
- [j71]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1028-1041 (2019) - 2018
- [j70]Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3020-3030 (2018) - 2017
- [j69]Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 683-693 (2017) - [j68]Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang:
Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1112-1125 (2017) - [j67]Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada:
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2949-2961 (2017) - 2016
- [j66]Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test 33(6): 7-14 (2016) - 2015
- [j65]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015) - [j64]Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1050-1062 (2015) - [j63]Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1063-1076 (2015) - 2014
- [j62]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 167 (2014) - [j61]Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast:
Cell-Aware Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1396-1409 (2014) - 2013
- [j60]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test 30(1): 68-76 (2013) - [j59]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1776-1786 (2013) - 2012
- [j58]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1894-1907 (2012) - 2011
- [j57]Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer:
Ring Generator: An Ultimate Linear Feedback Shift Register. Computer 44(6): 64-71 (2011) - [j56]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electron. Test. 27(5): 599-609 (2011) - [j55]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1072-1085 (2011) - [j54]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer:
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1225-1238 (2011) - 2010
- [j53]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 117-126 (2010) - [j52]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 441-453 (2010) - 2009
- [j51]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 245-258 (2009) - [j50]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1742-1755 (2009) - 2008
- [j49]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 147-159 (2008) - [j48]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 932-945 (2008) - [j47]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1278-1290 (2008) - 2007
- [j46]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24(3): 268-275 (2007) - [j45]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24(5): 476-485 (2007) - [j44]Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer:
Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electron. Test. 23(1): 35-45 (2007) - [j43]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing delay fault coverage through low-power segmented scan. IET Comput. Digit. Tech. 1(3): 220-229 (2007) - [j42]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Fault Diagnosis With Convolutional Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1478-1494 (2007) - 2006
- [j41]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
High Performance Dense Ring Generators. IEEE Trans. Computers 55(1): 83-87 (2006) - [j40]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 558-575 (2006) - 2005
- [j39]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 622-634 (2005) - [j38]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1315-1325 (2005) - 2004
- [j37]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee:
Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 776-792 (2004) - [j36]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Ring generators - new devices for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1306-1320 (2004) - 2003
- [j35]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
2D Test Sequence Generators. IEEE Des. Test Comput. 20(1): 51-59 (2003) - [j34]Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20(5): 17-25 (2003) - [j33]Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. 20(5): 58-66 (2003) - [j32]Janusz Rajski, Jerzy Tyszer:
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. J. Electron. Test. 19(6): 645-657 (2003) - 2001
- [j31]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Testing Schemes for FIR Filter Structures. IEEE Trans. Computers 50(7): 674-688 (2001) - 2000
- [j30]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 878-893 (2000) - [j29]Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska:
Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1052-1064 (2000) - [j28]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1175-1188 (2000) - 1999
- [j27]Janusz Rajski, Jerzy Tyszer:
Testing of telecommunications hardware [Guest Editorial]. IEEE Commun. Mag. 37(6): 60-62 (1999) - [j26]Janusz Rajski, Jerzy Tyszer:
Diagnosis of Scan Cells in BIST Environment. IEEE Trans. Computers 48(7): 724-731 (1999) - 1998
- [j25]Janusz Rajski, Jerzy Tyszer, Nadime Zacharia:
Test Data Decompression for Multiple Scan Designs with Boundary Scan. IEEE Trans. Computers 47(11): 1188-1200 (1998) - 1997
- [j24]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers 46(7): 795-810 (1997) - [j23]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 528-543 (1997) - [j22]Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1358-1369 (1997) - 1996
- [j21]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer:
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. IEEE Trans. Computers 45(8): 939-949 (1996) - [j20]Janusz Rajski, Jerzy Tyszer:
On Linear Dependencies in Subspaces of LFSR-Generated Sequences. IEEE Trans. Computers 45(10): 1212-1216 (1996) - [j19]Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski:
A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1409-1423 (1996) - 1995
- [j18]Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. 12(2): 32-39 (1995) - [j17]Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois:
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers 44(2): 223-233 (1995) - [j16]Aiman H. El-Maleh, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 582-590 (1995) - 1994
- [j15]Henry Cox, Janusz Rajski:
On necessary and nonconflicting assignments in algorithmic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 515-530 (1994) - 1993
- [j14]Janusz Rajski, Jerzy Tyszer:
Accumulator-Based Compaction of Test Responses. IEEE Trans. Computers 42(6): 643-650 (1993) - [j13]Janusz Rajski, Jerzy Tyszer:
Recursive Pseudoexhaustive Test Pattern Generation. IEEE Trans. Computers 42(12): 1517-1521 (1993) - [j12]Fadi Maamari, Janusz Rajski:
The dynamic reduction of fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 137-148 (1993) - [j11]Janusz Rajski, Jerzy Tyszer:
Test responses compaction in accumulators with rotate carry adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 531-539 (1993) - 1992
- [j10]Ashish Pancholy, Janusz Rajski, Larry J. McNaughton:
Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. IEEE Des. Test Comput. 9(1): 72-83 (1992) - [j9]Janusz Rajski, Jagadeesh Vasudevamurthy:
The testability-preserving concurrent decomposition and factorization of Boolean expressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 778-793 (1992) - [j8]Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski:
BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10): 1278-1288 (1992) - 1991
- [j7]Janusz Rajski, Jerzy Tyszer:
On the diagnostic properties of linear feedback shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(10): 1316-1322 (1991) - 1990
- [j6]Fadi Maamari, Janusz Rajski:
A method of fault simulation based on stem regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 212-220 (1990) - 1988
- [j5]Henry Cox, Janusz Rajski:
A method of fault analysis for test generation and fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(7): 813-833 (1988) - 1987
- [j4]Janusz Rajski, Vinod K. Agarwal:
Testing and Applications of Inverter-Free PLAs. IEEE Des. Test 4(6): 30-40 (1987) - 1986
- [j3]Janusz Rajski, Jerzy Tyszer:
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. IEEE Trans. Computers 35(1): 81-85 (1986) - 1985
- [j2]Janusz Rajski, Jerzy Tyszer:
Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. IEEE Trans. Computers 34(6): 549-553 (1985) - 1980
- [j1]Andrzej Jajszczyk, Janusz Rajski:
The Effect of Choosing the Switches for Rearrangements in Switching Networks. IEEE Trans. Commun. 28(10): 1832-1834 (1980)
Conference and Workshop Papers
- 2023
- [c204]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hybrid Ring Generators for In-System Test Applications. ETS 2023: 1-6 - 2022
- [c203]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Masking for In-System Deterministic Test. ETS 2022: 1-6 - [c202]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
DIST: Deterministic In-System Test with X-masking. ITC 2022: 20-27 - [c201]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Test Generation for an Iterative Design Flow with RTL Changes. ITC 2022: 305-313 - [c200]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hardware Root of Trust for SSN-basedDFT Ecosystems. ITC 2022: 479-483 - [c199]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Fast Test Generation for Structurally Similar Circuits. VTS 2022: 1-7 - [c198]Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS 2022: 1-7 - 2021
- [c197]Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compaction-Based MRAM Fault Diagnosis. ETS 2021: 1-6 - [c196]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
On Reduction of Deterministic Test Pattern Sets. ITC 2021: 260-267 - 2020
- [c195]Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer:
Test Sequence-Optimized BIST for Automotive Applications. ETS 2020: 1-6 - [c194]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski:
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS 2020: 1-2 - [c193]Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant:
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC 2020: 1-10 - [c192]Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak:
X-Tolerant Tunable Compactor for In-System Test. ITC 2020: 1-10 - [c191]Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada:
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC 2020: 1-10 - [c190]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng:
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia 2020: 130-135 - [c189]Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer:
Effective Design of Layout-Friendly EDT Decompressor. VTS 2020: 1-6 - 2019
- [c188]Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki:
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC 2019: 1-10 - [c187]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS 2019: 1-6 - 2018
- [c186]Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Hypercompression of Test Patterns. ITC 2018: 1-9 - [c185]Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski:
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. ITC 2018: 1-10 - [c184]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for In-System Automotive Test. ITC 2018: 1-9 - [c183]Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Class of Test Points and Their Applications. ITC 2018: 1-9 - [c182]Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer:
Staggered ATPG with capture-per-cycle observation test points. VTS 2018: 1-6 - 2017
- [c181]Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
ROM fault diagnosis for O(n2) test algorithms. ETS 2017: 1-6 - [c180]Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Full-scan LBIST with capture-per-cycle hybrid test points. ITC 2017: 1-9 - 2016
- [c179]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On Test Points Enhancing Hardware Security. ATS 2016: 61-66 - [c178]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS 2016: 1-6 - [c177]Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. ITC 2016: 1-7 - [c176]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Test point insertion in hybrid test compression/LBIST architectures. ITC 2016: 1-10 - [c175]Nilanjan Mukherjee, Janusz Rajski:
Digital Testing of ICs for Automotive Applications. VLSID 2016: 14-16 - 2015
- [c174]Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang:
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS 2015: 19-24 - [c173]Xijiang Lin, Wu-Tung Cheng, Janusz Rajski:
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS 2015: 97-102 - [c172]Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada:
Design for low test pattern counts. DAC 2015: 136:1-136:6 - [c171]Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Embedded deterministic test points for compact cell-aware tests. ITC 2015: 1-8 - [c170]Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
A deterministic BIST scheme based on EDT-compressed test patterns. ITC 2015: 1-8 - [c169]Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski:
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW 2015: 11-16 - [c168]Kun-Han Tsai, Janusz Rajski:
Clock-domain-aware test for improving pattern compression. VLSI-DAT 2015: 1-4 - [c167]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID 2015: 399-404 - [c166]Janusz Rajski, Nilanjan Mukherjee:
Innovative practices session 11C: Advanced scan methodologies [3 presentations]. VTS 2015: 1 - 2014
- [c165]Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS 2014: 74-80 - [c164]Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Test Compression with Programmable Broadcast-Based Control. ATS 2014: 174-179 - [c163]Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Using Implied Values in EDT-based Test Compression. DAC 2014: 11:1-11:6 - [c162]Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada:
Quality assurance in memory built-in self-test tools. DDECS 2014: 39-44 - [c161]Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski:
Cell-aware experiences in a high-quality automotive test suite. ETS 2014: 1-6 - [c160]Xijiang Lin, Mark Kassab, Janusz Rajski:
Using dynamic shift to reduce test data volume in high-compression designs. ETS 2014: 1-6 - [c159]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - [c158]Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung:
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW 2014: 22-31 - [c157]Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda:
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS 2014: 1-2 - 2013
- [c156]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht:
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium 2013: 201-206 - [c155]Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
New test compression scheme based on low power BIST. ETS 2013: 1-6 - [c154]Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. ITC 2013: 1-10 - [c153]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang:
On the generation of compact test sets. ITC 2013: 1-10 - [c152]Janusz Rajski, Jerzy Tyszer:
Fault diagnosis of TSV-based interconnects in 3-D stacked designs. ITC 2013: 1-9 - [c151]Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC 2013 - 2012
- [c150]Xijiang Lin, Janusz Rajski:
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium 2012: 83-88 - [c149]Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski:
Bandwidth-aware test compression logic for SoC designs. ETS 2012: 1-6 - [c148]Dariusz Czysz, Janusz Rajski, Jerzy Tyszer:
Low power test application with selective compaction in VLSI designs. ITC 2012: 1-10 - [c147]Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski:
Cell-aware Production test results from a 32-nm notebook processor. ITC 2012: 1-9 - [c146]Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
Low power programmable PRPG with enhanced fault coverage gradient. ITC 2012: 1-9 - [c145]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie:
Test generator with preselected toggling for low power built-in self-test. VTS 2012: 1-6 - 2011
- [c144]Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer:
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium 2011: 84-89 - [c143]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272 - [c142]Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek:
Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium 2011: 419-424 - [c141]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516 - [c140]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS 2011: 1-6 - [c139]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Reduced ATE Interface for High Test Data Compression. ETS 2011: 99-104 - [c138]Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers:
Cell-aware analysis for small-delay effects and production test results from different fault models. ITC 2011: 1-8 - [c137]Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9 - [c136]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy:
Low power compression utilizing clock-gating. ITC 2011: 1-8 - 2010
- [c135]Xijiang Lin, Janusz Rajski:
Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium 2010: 355-360 - [c134]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Diagnosis of failing scan cells through orthogonal response compaction. ETS 2010: 221-226 - [c133]Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274 - [c132]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer:
Low power compression of incompatible test cubes. ITC 2010: 704-713 - [c131]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - [c130]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab:
At-speed scan test with low switching activity. VTS 2010: 177-182 - 2009
- [c129]Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium 2009: 183-186 - [c128]Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
A scalable method for the generation of small test sets. DATE 2009: 1136-1141 - [c127]Janusz Rajski:
We Have Got Compression, What Next? ETS 2009 - [c126]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Compression based on deterministic vector clustering of incompatible test cubes. ITC 2009: 1-10 - [c125]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Fault diagnosis for embedded read-only memories. ITC 2009: 1-10 - [c124]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design 2009: 23-25 - [c123]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design 2009: 275-280 - [c122]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Highly X-Tolerant Selective Compaction of Test Responses. VTS 2009: 245-250 - 2008
- [c121]Xijiang Lin, Janusz Rajski:
Test Power Reduction by Blocking Scan Cell Outputs. ATS 2008: 329-336 - [c120]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393 - [c119]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253 - [c118]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - [c117]Xijiang Lin, Janusz Rajski:
Test Generation for Interconnect Opens. ITC 2008: 1-7 - [c116]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC 2008: 1-10 - 2007
- [c115]Xijiang Lin, Mark Kassab, Janusz Rajski:
Test Generation for Timing-Critical Transition Faults. ATS 2007: 493-500 - [c114]Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications. DAC 2007: 539-544 - [c113]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski:
Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693 - [c112]Janusz Rajski:
Logic Diagnosis and Yield Learning. DDECS 2007: 19 - [c111]Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware:
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. ETS 2007: 145-150 - [c110]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798 - [c109]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Embedded Deterministic Test. VTS 2007: 75-83 - [c108]Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware:
Silicon Evaluation of Static Alternative Fault Models. VTS 2007: 265-270 - 2006
- [c107]Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS 2006: 139-146 - [c106]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo:
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS 2006: 153-162 - [c105]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404 - [c104]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Test response compactor with programmable selector. DAC 2006: 1089-1094 - [c103]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan. ETS 2006: 21-28 - [c102]Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compactors with Variable Polynomials. ETS 2006: 117-122 - [c101]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472 - [c100]Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen:
Diagnosis with Limited Failure Information. ITC 2006: 1-10 - [c99]Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware:
A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC 2006: 1-10 - [c98]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10 - [c97]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10 - [c96]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10 - [c95]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424 - [c94]Xijiang Lin, Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing. VTS 2006: 2-7 - [c93]Wojciech Rajski, Janusz Rajski:
Modular Compactor of Test Responses. VTS 2006: 242-251 - [c92]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348 - 2005
- [c91]Xijiang Lin, Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults. ASP-DAC 2005: 178-183 - [c90]Janusz Rajski:
Embedded Test Technology - Brief History, Current Status, and Future Directions. Asian Test Symposium 2005 - [c89]Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz:
Defect Aware Test Patterns. DATE 2005: 450-455 - [c88]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker:
A unified fault model and test generation procedure for interconnect opens and bridges. ETS 2005: 22-27 - [c87]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Convolutional compaction-driven diagnosis of scan failures. ETS 2005: 176-181 - [c86]Janusz Rajski:
Test compression - real issues and matching solutions. ITC 2005: 2 - [c85]Yu Huang, Wu-Tung Cheng, Janusz Rajski:
Compressed pattern diagnosis for scan chain failures. ITC 2005: 8 - [c84]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Diagnosis with convolutional compactors in presence of unknown states. ITC 2005: 10 - [c83]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64 - [c82]Janusz Rajski, Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors. VTS 2005: 114-119 - 2004
- [c81]Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski:
Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209 - [c80]Janusz Rajski, Kan Thapar:
Nanometer Design: What are the Requirements for Manufacturing Test? DATE 2004: 930-937 - [c79]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects. ICCD 2004: 192-199 - [c78]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490 - [c77]Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors. ITC 2004: 498-507 - [c76]Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533 - [c75]Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski:
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294 - [c74]Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23 - [c73]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Planar High Performance Ring Generators. VTS 2004: 193-198 - 2003
- [c72]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862 - [c71]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198- - [c70]Janusz Rajski, Jerzy Tyszer:
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. ICCD 2003: 331- - [c69]Janusz Rajski:
Test Challenges of Nanometer Technology. ITC 2003: 13-22 - [c68]Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338 - [c67]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Convolutional Compaction of Test Responses. ITC 2003: 745-754 - [c66]Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski:
Impact of Multiple-Detect Test Patterns on Product Quality. ITC 2003: 1031-1040 - [c65]Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski:
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220 - [c64]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
High Speed Ring Generators and Compactors of Test Data. VTS 2003: 57-62 - 2002
- [c63]Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116 - [c62]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93 - [c61]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310 - [c60]Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski:
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. ASP-DAC/VLSI Design 2002: 604- - [c59]J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski:
Innovations in Test Automation. VTS 2002: 43-46 - 2001
- [c58]Janusz Rajski:
DFT for High-Quality Low Cost Manufacturing Test. Asian Test Symposium 2001: 3- - [c57]John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267 - [c56]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097 - [c55]John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298 - 2000
- [c54]Xiaoliang Bai, Sujit Dey, Janusz Rajski:
Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624 - [c53]Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463 - [c52]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS 2000: 377-388 - 1999
- [c51]Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski:
Logic BIST for large industrial designs: real issues and case studies. ITC 1999: 358-367 - [c50]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
Synthesis of pattern generators based on cellular automata with phase shifters. ITC 1999: 368-377 - [c49]Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska:
STAR-ATPG: a high speed test pattern generator for large scan designs. ITC 1999: 1021-1030 - [c48]Janusz Rajski, Jerzy Tyszer, Sanjay Patel:
Built-In Self-Test for Systems on Silicon. VLSI Design 1999: 609-610 - [c47]Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer:
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS 1999: 236-245 - 1998
- [c46]Aiman H. El-Maleh, Mark Kassab, Janusz Rajski:
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC 1998: 625-631 - [c45]Janusz Rajski, Jerzy Tyszer:
Modular logic built-in self-test for IP cores. ITC 1998: 313-321 - [c44]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of large phase shifters for built-in self-test. ITC 1998: 1047-1056 - [c43]Janusz Rajski, Jerzy Tyszer:
Design of Phase Shifters for BIST Applications. VTS 1998: 218-224 - 1997
- [c42]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477 - [c41]Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556 - [c40]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Parameterizable Testing Scheme for FIR Filters. ITC 1997: 694-703 - [c39]Janusz Rajski, Jerzy Tyszer:
Fault Diagnosis in Scan-Based BIST. ITC 1997: 894-902 - [c38]J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian:
Systems On Silicon: Design and Test Challenges. VTS 1997: 184-185 - 1996
- [c37]Janusz Rajski, Jerzy Tyszer:
Multiplicative Window Generators of Pseudo-random Test Vectors. ED&TC 1996: 42-49 - [c36]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski:
Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC 1996: 186-194 - [c35]Nagesh Tamarapalli, Janusz Rajski:
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. ITC 1996: 649-658 - [c34]Fidel Muradali, Janusz Rajski:
A self-driven test structure for pseudorandom testing of non-scan sequential circuits. VTS 1996: 17-25 - [c33]J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507 - 1995
- [c32]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
On Test Set Preservation of Retimed Circuits. DAC 1995: 176-182 - [c31]Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338 - [c30]Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski:
Complexity of sequential ATPG. ED&TC 1995: 252-261 - [c29]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On testable multipliers for fixed-width data path architectures. ICCAD 1995: 541-547 - [c28]Mark Kassab, Janusz Rajski, Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605 - [c27]Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self test for high-level synthesis. VTS 1995: 132-139 - [c26]Marc D. Riedel, Janusz Rajski:
Fault coverage analysis of RAM test algorithms. VTS 1995: 227-234 - [c25]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer:
Decompression of test data using variable-length seed LFSRs. VTS 1995: 426-433 - 1994
- [c24]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer:
Test pattern generation based on arithmetic operations. ICCAD 1994: 117-124 - [c23]Aiman El-Maleh, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. VTS 1994: 15-21 - 1992
- [c22]Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski:
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. ITC 1992: 120-129 - [c21]Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh:
Recent advances in logic synthesis with testability. VTS 1992: 254-256 - 1991
- [c20]Stephen Pateras, Janusz Rajski:
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. DAC 1991: 347-352 - [c19]Stephen Pateras, Janusz Rajski:
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. ITC 1991: 473-482 - 1990
- [c18]Janusz Rajski, Jerzy Tyszer, Babak Salimi:
On the Diagnostic Resolution of Signature Analysis. ICCAD 1990: 364-367 - [c17]Jagadeesh Vasudevamurthy, Janusz Rajski:
A Method for Concurrent Decomposition and Factorization of Boolean Expressions. ICCAD 1990: 510-513 - [c16]Janusz Rajski, Henry Cox:
A method to calculate necessary assignments in algorithmic test pattern generation. ITC 1990: 25-34 - [c15]Janusz Rajski, Jagadeesh Vasudevamurthy:
Testability preserving transformations in multi-level logic synthesis. ITC 1990: 265-273 - [c14]Fadi Maamari, Janusz Rajski:
The dynamic reduction of fault simulation. ITC 1990: 801-808 - [c13]Ashish Pancholy, Janusz Rajski, Larry J. McNaughton:
Empirical failure analysis and validation of fault models in CMOS VLSI. ITC 1990: 938-947 - 1989
- [c12]Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie:
Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC 1989: 700-711 - 1988
- [c11]Fadi Maamari, Janusz Rajski:
A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits. FTCS 1988: 122-127 - [c10]Janusz Rajski:
GEMINI-a logic system for fault diagnosis based on set functions. FTCS 1988: 292-297 - [c9]Fadi Maamari, Janusz Rajski:
A fault simulation method based on stem regions. ICCAD 1988: 170-173 - [c8]Eli Chiprout, Janusz Rajski, Markus Robinson:
Parallel PLA fault simulation based on Boolean vector operations. ICCAD 1988: 194-197 - [c7]Stephen Pateras, Janusz Rajski:
A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. ICCD 1988: 560-563 - [c6]Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski:
Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. ITC 1988: 126-137 - [c5]Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski:
On Multiple Fault Coverage and Aliasing Probability Measures. ITC 1988: 314-321 - [c4]Henry Cox, Janusz Rajski:
Stuck-Open and Transition Fault Testing in CMOS Complex Gates. ITC 1988: 688-694 - [c3]Markus Robinson, Janusz Rajski:
An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. ITC 1988: 784-795 - 1985
- [c2]Vinod K. Agarwal, Janusz Rajski:
Testing Properties and Applications of Inverter-Free PLA's. ITC 1985: 500-507 - 1984
- [c1]Janusz Rajski, Jerzy Tyszer:
The detection of small size multiple faults by single fault test sets n programmable logic arrays. Fehlertolerierende Rechensysteme 1984: 417-425
Editorship
- 2007
- [e1]Jill Sibert, Janusz Rajski:
2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007. IEEE Computer Society 2007, ISBN 1-4244-1128-9 [contents]
Coauthor Index
[j82] [j80] [j77] [j75] [j74] [j69] [j68] [j64] [j63] [j62] [j60] [j59] [j58] [j57] [j56] [j54] [j53] [j50] [j49] [j47] [j45] [j44] [j42] [j41] [j36] [j35] [j30] [c203] [c202] [c195] [c192] [c187] [c174] [c170] [c165] [c164] [c163] [c155] [c149] [c146] [c145] [c144] [c142] [c140] [c139] [c137] [c134] [c133] [c132] [c126] [c122] [c118] [c114] [c109] [c104] [c97] [c87] [c84] [c77] [c73] [c64] [c61] [c52] [c50] [c47]
[j84] [j80] [j76] [j75] [j73] [j71] [j70] [j67] [j66] [j65] [j64] [j63] [j62] [j60] [j59] [j58] [j57] [j55] [j54] [j53] [j52] [j49] [j45] [j41] [j37] [j33] [j31] [j24] [c201] [c199] [c195] [c192] [c189] [c188] [c184] [c180] [c179] [c177] [c176] [c175] [c172] [c171] [c166] [c165] [c163] [c159] [c155] [c154] [c146] [c142] [c141] [c139] [c137] [c133] [c132] [c131] [c126] [c125] [c124] [c123] [c122] [c116] [c97] [c74] [c73] [c65] [c61] [c40] [c31] [c29] [c27]
[j85] [j83] [j82] [j81] [j80] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [j67] [j66] [j65] [j64] [j63] [j62] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [j52] [j50] [j49] [j47] [j45] [j44] [j42] [j41] [j39] [j37] [j36] [j35] [j33] [j32] [j31] [j30] [j28] [j27] [j26] [j25] [j24] [j22] [j21] [j20] [j14] [j13] [j11] [j7] [j3] [j2] [c204] [c203] [c202] [c200] [c197] [c196] [c195] [c192] [c188] [c187] [c186] [c184] [c183] [c182] [c181] [c180] [c179] [c177] [c176] [c174] [c172] [c171] [c170] [c165] [c164] [c163] [c162] [c159] [c155] [c154] [c152] [c149] [c148] [c146] [c145] [c144] [c142] [c141] [c140] [c139] [c137] [c134] [c133] [c132] [c126] [c125] [c124] [c123] [c122] [c118] [c116] [c114] [c109] [c104] [c102] [c97] [c87] [c84] [c83] [c82] [c77] [c74] [c73] [c72] [c70] [c67] [c64] [c61] [c52] [c50] [c48] [c47] [c45] [c44] [c43] [c40] [c39] [c37] [c36] [c31] [c29] [c28] [c27] [c25] [c24] [c18] [c1]
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