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Takashi Sato 0001
Person information
- affiliation: Kyoto University, Department of Communication and Computer Engineering, Sakyo, Kyoto, Japan
Other persons with the same name
- Takashi Sato — disambiguation page
- Takashi Sato 0002 — National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan
- Takashi Sato 0003 — Tohoku University, Sendai, Japan
- Takashi Sato 0004 — Kumamoto University, Kumamoto, Japan
- Takashi Sato 0005 — Osaka Kyoiku University, Kashiwara, Japan
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2020 – today
- 2024
- [c92]Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. DATE 2024: 1-6 - [c91]Takefumi Koike, Hiromitsu Awano, Takashi Sato:
DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder. DATE 2024: 1-2 - 2023
- [j65]Takumi Hara, Takashi Sato, Tetsuya Ogata, Hiromitsu Awano:
Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation. IEEE Robotics Autom. Lett. 8(10): 6435-6442 (2023) - [j64]Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. ACM Trans. Embed. Comput. Syst. 22(5s): 110:1-110:20 (2023) - [c90]Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang:
Invited Paper: Overview of 2023 CAD Contest at ICCAD. ICCAD 2023: 1-6 - [c89]Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani:
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. ITC 2023: 132-140 - [i11]Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. CoRR abs/2307.11094 (2023) - 2022
- [j63]Tianchen Wang, Jiawei Zhang, Jinjun Xiong, Song Bian, Zheyu Yan, Meiping Huang, Jian Zhuang, Takashi Sato, Xiaowei Xu, Yiyu Shi:
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. IEEE Trans. Computers 71(11): 2717-2727 (2022) - [j62]Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3650-3660 (2022) - [j61]Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato:
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5515-5525 (2022) - [c88]Takamochi Kanda, Takashi Sato, Hiromitsu Awano, Sota Kondo, Koji Yamamoto:
Respiratory Rate Estimation Based on WiFi Frame Capture. CCNC 2022: 881-884 - [c87]Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato:
Overview of 2022 CAD Contest at ICCAD. ICCAD 2022: 92:1-92:3 - [c86]Masato Shiozaki, Takashi Sato:
Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Their Recovery. IRPS 2022: 64-1 - [i10]Kyohei Shimozato, Michihiro Shintani, Takashi Sato:
Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. CoRR abs/2201.10126 (2022) - 2021
- [j60]Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato:
APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations. IEEE Trans. Inf. Forensics Secur. 16: 4663-4678 (2021) - [c85]Itsuki Shirakami, Takashi Sato:
Heart Rate Variability Extraction using Commodity Wi-Fi Devices via Time Domain Signal Processing. BHI 2021: 1-4 - [c84]Suraj Hebbar, Takashi Sato:
Motion Robust Remote Photoplethysmography via Frequency Domain Motion Artifact Reduction. BioCAS 2021: 1-4 - [c83]Kotaro Matsuoka, Yusuke Hoshizuki, Takashi Sato, Song Bian:
Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE. WAHC@CCS 2021: 63-68 - [c82]Song Bian, Weiwen Jiang, Takashi Sato:
Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment. DAC 2021: 1347-1350 - [c81]Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato:
Overview of 2021 CAD Contest at ICCAD. ICCAD 2021: 1-3 - [c80]Tatsuki Ono, Song Bian, Takashi Sato:
Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. ISCAS 2021: 1-5 - [c79]Takashi Sato, Yuki Tanaka, Song Bian:
Clonable PUF: on the Design of PUFs That Share Equivalent Responses. ISCAS 2021: 1-5 - [c78]Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato, Song Bian:
Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE. USENIX Security Symposium 2021: 4007-4024 - [i9]Michihiro Shintani, Aoi Ueda, Takashi Sato:
Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. CoRR abs/2110.15048 (2021) - [i8]Tatsuki Ono, Song Bian, Takashi Sato:
Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. IACR Cryptol. ePrint Arch. 2021: 198 (2021) - [i7]Takashi Sato, Yuki Tanaka, Song Bian:
Clonable PUF: On the Design of PUFs That Share Equivalent Responses. IACR Cryptol. ePrint Arch. 2021: 341 (2021) - [i6]Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato:
APAS: Application-Specific Accelerators for RLWE-based Homomorphic Linear Transformations. IACR Cryptol. ePrint Arch. 2021: 1284 (2021) - 2020
- [j59]Yue Zheng, Xiaojin Zhao, Takashi Sato, Yuan Cao, Chip-Hong Chang:
Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System. IEEE Trans. Inf. Forensics Secur. 15: 2824-2839 (2020) - [c77]Yuki Kume, Song Bian, Takashi Sato:
A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation. ASP-DAC 2020: 458-463 - [c76]Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato:
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. ATS 2020: 1-6 - [c75]Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato:
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. ATS 2020: 1-6 - [c74]Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato:
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CVPR 2020: 9400-9409 - [c73]Akira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian, Takashi Sato:
Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver. DAC 2020: 1-6 - [c72]Song Bian, Weiwen Jiang, Qing Lu, Yiyu Shi, Takashi Sato:
NASS: Optimizing Secure Inference via Neural Architecture Search. ECAI 2020: 1746-1753 - [c71]Song Bian, Xiaowei Xu, Weiwen Jiang, Yiyu Shi, Takashi Sato:
BUNET: Blind Medical Image Segmentation Based on Secure UNET. MICCAI (2) 2020: 612-622 - [i5]Song Bian, Weiwen Jiang, Qing Lu, Yiyu Shi, Takashi Sato:
NASS: Optimizing Secure Inference via Neural Architecture Search. CoRR abs/2001.11854 (2020) - [i4]Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato:
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CoRR abs/2003.05328 (2020) - [i3]Song Bian, Xiaowei Xu, Weiwen Jiang, Yiyu Shi, Takashi Sato:
BUNET: Blind Medical Image Segmentation Based on Secure UNET. CoRR abs/2007.06855 (2020) - [i2]Kenta Nagura, Song Bian, Takashi Sato:
FedNNNN: Norm-Normalized Neural Network Aggregation for Fast and Accurate Federated Learning. CoRR abs/2008.04538 (2020) - [i1]Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato, Song Bian:
Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE. CoRR abs/2010.09410 (2020)
2010 – 2019
- 2019
- [j58]Song Bian, Masayuki Hiromoto, Takashi Sato:
Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(2): 430-439 (2019) - [j57]Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan:
GPU-based Ising computing for solving max-cut combinatorial optimization problems. Integr. 69: 335-344 (2019) - [c70]Song Bian, Masayuki Hiromoto, Takashi Sato:
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. ASP-DAC 2019: 621-626 - [c69]Masaki Nakamura, Takashi Sato:
Heart Rate Estimation during Exercise from Photoplethysmographic Signals Using Convolutional Neural Network. BioCAS 2019: 1-4 - [c68]Song Bian, Masayuki Hiromoto, Takashi Sato:
Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. DAC 2019: 113 - [c67]Song Bian, Masayuki Hiromoto, Takashi Sato:
DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. DATE 2019: 1739-1744 - 2018
- [j56]Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato:
Area Efficient Annealing Processor for Ising Model without Random Number Generator. IEICE Trans. Inf. Syst. 101-D(2): 314-323 (2018) - [j55]Masayuki Hiromoto, Motoki Yoshinaga, Takashi Sato:
MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1035-1044 (2018) - [j54]Satoshi Yamamori, Masayuki Hiromoto, Takashi Sato:
Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1092-1100 (2018) - [j53]Yuya Fujita, Masayuki Hiromoto, Takashi Sato:
PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. IEEE Trans. Biomed. Eng. 65(1): 189-198 (2018) - [j52]Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato:
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 602-606 (2018) - [c66]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC 2018: 631-636 - [c65]Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato:
Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. CVPR Workshops 2018: 616-624 - [c64]Song Bian, Masayuki Hiromoto, Takashi Sato:
DWE: decrypting learning with errors with errors. DAC 2018: 3:1-3:6 - [c63]Hiromitsu Awano, Takashi Sato:
Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs. DATE 2018: 1447-1452 - [c62]Yuya Fujita, Masayuki Hiromoto, Takashi Sato:
Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. EMBC 2018: 3024-3027 - [c61]Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato:
Enhancing the solution quality of hardware ising-model solver via parallel tempering. ICCAD 2018: 70 - [c60]Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED 2018: 251-256 - 2017
- [j51]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1464-1472 (2017) - [j50]Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2797-2806 (2017) - [j49]Hiromitsu Awano, Takashi Sato:
Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2807-2815 (2017) - [j48]Hiromitsu Awano, Shumpei Morita, Takashi Sato:
Scalable Device Array for Statistical Characterization of BTI-Related Parameters. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1455-1466 (2017) - [j47]Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao:
RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2248-2257 (2017) - [c59]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Efficient circuit failure probability calculation along product lifetime considering device aging. ASP-DAC 2017: 93-98 - [c58]Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang:
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC 2017: 543-548 - [c57]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC 2017: 66:1-66:6 - [c56]Song Bian, Masayuki Hiromoto, Takashi Sato:
SCAM: Secured content addressable memory based on homomorphic encryption. DATE 2017: 984-989 - [c55]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED 2017: 426-431 - 2016
- [j46]Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato:
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32(5): 601-609 (2016) - [j45]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1390-1399 (2016) - [j44]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1400-1409 (2016) - [c54]Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato:
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS 2016: 234-239 - [c53]Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato:
Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. CVPR Workshops 2016: 870-876 - [c52]Hiromitsu Awano, Takashi Sato:
Efficient transistor-level timing yield estimation via line sampling. DAC 2016: 115:1-115:6 - [c51]Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI 2016: 203-208 - [c50]Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. ISCAS 2016: 2619-2622 - [c49]Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato:
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED 2016: 307-312 - 2015
- [j43]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. 98-C(7): 741-750 (2015) - [j42]Yiyu Shi, Takashi Sato:
Introduction to: Special Issue on Cross-Layer System Design. ACM J. Emerg. Technol. Comput. Syst. 12(3): 20:1-20:2 (2015) - [c48]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. DATE 2015: 549-554 - 2014
- [j41]Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, Takashi Sato:
State-Dependence of On-Chip Power Distribution Network Capacitance. IEICE Trans. Electron. 97-C(1): 77-84 (2014) - [j40]Shiho Hagiwara, Takanori Date, Kazuya Masu, Takashi Sato:
Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. IEICE Trans. Electron. 97-C(4): 280-288 (2014) - [j39]Michihiro Shintani, Takashi Sato:
IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. IEICE Trans. Inf. Syst. 97-D(8): 2095-2104 (2014) - [j38]Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Automation of Model Parameter Estimation for Random Telegraph Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2383-2392 (2014) - [j37]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato:
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1056-1066 (2014) - [c47]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Variability in device degradations: Statistical observation of NBTI for 3996 transistors. ESSDERC 2014: 218-221 - [c46]Michihiro Shintani, Takashi Sato:
Sensorless estimation of global device-parameters based on Fmax testing. ICCAD 2014: 498-503 - [c45]Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi:
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. ISQED 2014: 428-433 - 2013
- [j36]Michihiro Shintani, Takashi Sato:
Device-Parameter Estimation through IDDQ Signatures. IEICE Trans. Inf. Syst. 96-D(2): 303-313 (2013) - [j35]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. 96-C(4): 454-462 (2013) - [j34]Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Trans. Electron. 96-C(4): 473-481 (2013) - [c44]Takashi Sato:
Statistical simulation methods for circuit performance analysis. ASICON 2013: 1-4 - [c43]Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Realization of frequency-domain circuit analysis through random walk. ASP-DAC 2013: 169-174 - [c42]Michihiro Shintani, Takashi Sato:
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC 2013: 614-619 - [c41]Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE 2013: 535-540 - [c40]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE 2013: 701-706 - [c39]Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. ACM Great Lakes Symposium on VLSI 2013: 95-100 - [c38]Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED 2013: 538-545 - [c37]Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Multi-trap RTN parameter extraction based on Bayesian inference. ISQED 2013: 597-602 - 2012
- [j33]Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2242-2250 (2012) - [j32]Takashi Enami, Takashi Sato, Masanori Hashimoto:
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2261-2271 (2012) - [j31]Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2272-2283 (2012) - [c36]Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao:
Statistical aging under dynamic voltage scaling: A logarithmic model approach. CICC 2012: 1-4 - [c35]Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao:
Physics matters: statistical aging prediction under trapping/detrapping. DAC 2012: 139-144 - [c34]Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi:
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED 2012: 306-311 - [c33]Michihiro Shintani, Takashi Sato:
A Bayesian-based process parameter estimation using IDDQ current signature. VTS 2012: 86-91 - 2011
- [c32]Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI 2011: 211-216 - [c31]Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED 2011: 785-790 - [c30]Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato:
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC 2011: 57-62 - 2010
- [j30]Takumi Uezono, Kazuya Masu, Takashi Sato:
A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. IEICE Trans. Electron. 93-C(3): 324-331 (2010) - [j29]Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato:
A Universal Equivalent Circuit Model for Ceramic Capacitors. IEICE Trans. Electron. 93-C(3): 347-354 (2010) - [j28]Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto:
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. 93-C(3): 388-392 (2010) - [j27]Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda:
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(9): 1605-1611 (2010) - [j26]Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato:
Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2409-2416 (2010) - [j25]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2524-2532 (2010) - [j24]Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 250-260 (2010) - [c29]Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD 2010: 703-708 - [c28]Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu:
Decomposition of drain-current variation into gain-factor and threshold voltage variations. ISCAS 2010: 1053-1056 - [c27]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556 - [c26]Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato:
Robust importance sampling for efficient SRAM yield analysis. ISQED 2010: 15-21 - [c25]Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato:
Linear time calculation of state-dependent power distribution network capacitance. ISQED 2010: 75-80 - [c24]Koh Yamanaga, Kazuya Masu, Takashi Sato:
Application of generalized scattering matrix for prediction of power supply noise. SLIP 2010: 83-90 - [c23]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC 2010: 248-253 - [c22]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Path clustering for adaptive test. VTS 2010: 15-20
2000 – 2009
- 2009
- [j23]Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa:
Physical design challenges to nano-CMOS circuits. IEICE Electron. Express 6(11): 703-720 (2009) - [j22]Koh Yamanaga, Takashi Sato, Kazuya Masu:
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 976-982 (2009) - [j21]Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 990-997 (2009) - [j20]Takumi Uezono, Takashi Sato, Kazuya Masu:
One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1024-1030 (2009) - [j19]Shiho Hagiwara, Takashi Sato, Kazuya Masu:
Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1031-1038 (2009) - [j18]Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto:
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3016-3023 (2009) - [j17]Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu:
Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. IEEE J. Solid State Circuits 44(11): 2977-2986 (2009) - [c21]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu:
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156 - 2008
- [j16]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Trans. Inf. Syst. 91-D(3): 655-660 (2008) - [j15]Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu:
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 951-956 (2008) - [j14]Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu:
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 957-964 (2008) - [j13]Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro:
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. 91-C(7): 1142-1150 (2008) - [c20]Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu:
Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC 2008: 518-523 - [c19]Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu:
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC 2008: 698-701 - [c18]Takashi Enami, Masanori Hashimoto, Takashi Sato:
Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425 - 2007
- [j12]Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto:
Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 808-814 (2007) - [j11]Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye:
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 868-872 (2007) - [c17]Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu:
A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC 2007: 118-119 - [c16]Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu:
Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI 2007: 513-516 - [c15]Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu:
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED 2007: 21-26 - [c14]Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu:
Weakness Identification for Effective Repair of Power Distribution Network. PATMOS 2007: 222-231 - [c13]Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu:
Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8 - 2006
- [j10]Koutaro Hachiya, Hiroyuki Kobayashi, Takaaki Okumura, Takashi Sato, Hiroki Oka:
A Method to Derive SSO Design Rule Considering Jitter Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 865-872 (2006) - [j9]Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto:
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3491-3499 (2006) - [c12]Norihide Okada, Chikaaki Kodama, Takashi Sato, Kunihiro Fujiyoshi:
Thermal Driven Module Placement Using Sequence-pair. APCCAS 2006: 1871-1874 - [c11]Takashi Sato, Yu Matsumoto, Koji Hirakimoto, Michio Komoda, Junichi Mano:
A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop. CICC 2006: 563-566 - [c10]Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye:
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. CICC 2006: 861-864 - 2005
- [j8]Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto:
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3382-3389 (2005) - [j7]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3429-3436 (2005) - [c9]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728 - [c8]Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto:
On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077 - [c7]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101 - 2004
- [j6]Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo:
Probabilistic crosstalk delay estimation for ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1377-1383 (2004) - 2003
- [j5]Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda:
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 841-845 (2003) - [j4]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2933-2941 (2003) - [j3]Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu:
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 560-572 (2003) - [c6]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximate formulae approach for efficient inductance extraction. ASP-DAC 2003: 143-148 - [c5]Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto:
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC 2003: 149-155 - [c4]Takashi Sato, Hiroo Masuda:
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. ISQED 2003: 395-400 - 2002
- [c3]Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC/VLSI Design 2002: 77- - 2001
- [j2]Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu:
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. IEEE J. Solid State Circuits 36(10): 1587-1591 (2001) - 2000
- [c2]Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu:
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC 2000: 201-204
1990 – 1999
- 1999
- [j1]Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome:
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. IEEE J. Solid State Circuits 34(5): 653-660 (1999)
1980 – 1989
- 1989
- [c1]R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu:
An efficient algorithm for layout compaction problem with symmetry constraints. ICCAD 1989: 148-151
Coauthor Index
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