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ORCIDAnand Raghunathan
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- affiliation: Purdue University, West Lafayette, USA
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2020 – today
- 2025
[i35]Reena Elangovan, Charbel Sakr, Anand Raghunathan, Brucek Khailany:
BCQ: Block Clustered Quantization for 4-bit (W4A4) LLM Inference. CoRR abs/2502.05376 (2025)- [i34]Jimmy Gammell, Anand Raghunathan, Abolfazl Hashemi, Kaushik Roy:
Learning to Localize Leakage of Cryptographic Sensitive Variables. CoRR abs/2503.07464 (2025) - 2024
- [j120]Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
MixTrain: accelerating DNN training via input mixing. Frontiers Artif. Intell. 7 (2024) - [j119]Abinand Nallathambi, Christin David Bose, Wilfried Haensch, Anand Raghunathan:
LRMP: Layer Replication with Mixed Precision for spatial in-memory DNN accelerators. Frontiers Artif. Intell. 7 (2024) - [j118]Surya Selvam
, Amrit Nagarajan, Anand Raghunathan:
Efficient Batched Inference in Conditional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 4081-4092 (2024) - [j117]Soumendu Kumar Ghosh, Arnab Raha, Vijay Raghunathan, Anand Raghunathan:
PArtNNer: Platform-Agnostic Adaptive Edge-Cloud DNN Partitioning for Minimizing End-to-End Latency. ACM Trans. Embed. Comput. Syst. 23(1): 6:1-6:38 (2024) - [c219]Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan:
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. DAC 2024: 336:1-336:6 - [c218]Amrit Nagarajan, Anand Raghunathan:
Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks. ECML/PKDD (5) 2024: 73-88 - [i33]Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan:
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. CoRR abs/2403.15717 (2024) - [i32]Niharika Thakuria, Akul Malhotra, Sandeep Krishna Thirumala, Reena Elangovan, Anand Raghunathan, Sumeet Kumar Gupta:
SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks. CoRR abs/2408.13617 (2024) - [i31]Jimmy Gammell, Anand Raghunathan, Kaushik Roy:
Power side-channel leakage localization through adversarial training of deep neural networks. CoRR abs/2410.22425 (2024) - 2023
- [j116]Amrit Nagarajan, Anand Raghunathan:
FASTRAIN-GNN: Fast and Accurate Self-Training for Graph Neural Networks. Trans. Mach. Learn. Res. 2023 (2023) - [j115]Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan:
X-Former: In-Memory Acceleration of Transformers. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1223-1233 (2023) - [c217]Amrit Nagarajan, Anand Raghunathan:
TokenDrop + BucketSampler: Towards Efficient Padding-free Fine-tuning of Language Models. EMNLP (Findings) 2023: 11682-11695 - [c216]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems. SOCC 2023: 1-6 - [i30]Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan:
X-Former: In-Memory Acceleration of Transformers. CoRR abs/2303.07470 (2023) - [i29]Sourjya Roy, Cheng Wang, Anand Raghunathan:
Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators. CoRR abs/2308.02024 (2023) - [i28]Abinand Nallathambi, Christin David Bose, Wilfried Haensch, Anand Raghunathan:
LRMP: Layer Replication with Mixed Precision for Spatial In-memory DNN Accelerators. CoRR abs/2312.03146 (2023) - [i27]Amrit Nagarajan, Anand Raghunathan:
Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks. CoRR abs/2312.12385 (2023) - 2022
- [j114]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems. ACM Trans. Embed. Comput. Syst. 21(5): 55:1-55:29 (2022) - [j113]Reena Elangovan, Shubham Jain, Anand Raghunathan:
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration. ACM Trans. Design Autom. Electr. Syst. 27(3): 28:1-28:20 (2022) - [j112]Mustafa Fayez Ali, Sourjya Roy, Utkarsh Saxena, Tanvi Sharma, Anand Raghunathan, Kaushik Roy:
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1615-1630 (2022) - [c215]Amrit Nagarajan, Jacob R. Stevens, Anand Raghunathan:
Efficient ensembles of graph neural networks. DAC 2022: 187-192 - [c214]Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan:
Efficiency attacks on spiking neural networks. DAC 2022: 373-378 - [c213]Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy:
A cross-layer approach to cognitive computing: invited. DAC 2022: 1327-1330 - [c212]Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis:
Approximate Computing and the Efficient Machine Learning Expedition. ICCAD 2022: 80:1-80:9 - [c211]Aradhana Mohan Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan:
Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks. ICCAD 2022: 153:1-153:9 - [c210]Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan:
AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models. IJCNN 2022: 1-8 - [c209]Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan:
Layerwise Disaggregated Evaluation of Spiking Neural Networks. ISLPED 2022: 25:1-25:6 - [c208]Reena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan:
Energy Efficient Cache Design with Piezoelectric FETs. ISLPED 2022: 31:1-31:6 - [p3]Sourav Sanyal, Shubham Negi, Anand Raghunathan, Kaushik Roy:
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective. Approximate Computing 2022: 365-395 - [i26]Niharika Thakuria, Reena Elangovan, Sandeep Krishna Thirumala, Anand Raghunathan, Sumeet Kumar Gupta:
STeP-CiM: Strain-enabled Ternary Precision Computation-in-Memory based on Non-Volatile 2D Piezoelectric Transistors. CoRR abs/2203.16416 (2022) - [i25]Wilfried Haensch, Anand Raghunathan, Kaushik Roy, Bhaswar Chakrabarti, Charudatta M. Phatak, Cheng Wang, Supratik Guha:
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks. CoRR abs/2206.08735 (2022) - [i24]Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis:
Approximate Computing and the Efficient Machine Learning Expedition. CoRR abs/2210.00497 (2022) - 2021
- [j111]Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan:
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 701-710 (2021) - [j110]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 326-338 (2021) - [j109]Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan:
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 730-738 (2021) - [c207]Indranil Chakraborty, Sourjya Roy, Shrihari Sridharan, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Anand Raghunathan:
Design Tools for Resistive Crossbar based Machine Learning Accelerators. AICAS 2021: 1-4 - [c206]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems. AICAS 2021: 1-4 - [c205]Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan:
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC 2021: 469-474 - [c204]Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan:
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks. DAC 2021: 955-960 - [c203]Younghoon Kim, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan:
Value Similarity Extensions for Approximate Computing in General-Purpose Processors. DATE 2021: 481-486 - [c202]Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
Efficacy of Pruning in Ultra-Low Precision DNNs. ISLPED 2021: 1-6 - [i23]Malin Prematilake, Younghyun Kim, Vijay Raghunathan, Anand Raghunathan, Niraj K. Jha:
HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices. CoRR abs/2103.01781 (2021) - [i22]Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan:
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR abs/2103.09301 (2021) - [i21]Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan:
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks. CoRR abs/2103.10836 (2021) - [i20]Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan:
PIM-DRAM: Accelerating Machine Learning Workloads using Processing in Commodity DRAM. CoRR abs/2105.03736 (2021) - 2020
- [j108]Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy:
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks. IEEE Access 8: 171924-171932 (2020) - [j107]Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan, Amogh Agrawal, Anand Raghunathan, Kaushik Roy:
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges. Proc. IEEE 108(12): 2276-2310 (2020) - [j106]Swagath Venkataramani, Vivek Joy Kozhikkottu, Amit Sabne, Kaushik Roy, Anand Raghunathan:
Logic Synthesis of Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2503-2515 (2020) - [j105]Sarada Krithivasan, Sanchari Sen, Anand Raghunathan:
Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4129-4141 (2020) - [j104]Shubham Jain, Anand Raghunathan:
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems. ACM Trans. Embed. Comput. Syst. 18(6): 113:1-113:23 (2020) - [j103]Sanjay Ganapathy, Swagath Venkataramani, Giridhur Sriraman, Balaraman Ravindran, Anand Raghunathan:
DyVEDeep: Dynamic Variable Effort Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 19(3): 16:1-16:24 (2020) - [j102]Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan:
Approximate Memory Compression. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 980-991 (2020) - [j101]Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1567-1577 (2020) - [c201]Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks. DATE 2020: 31-36 - [c200]Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan:
Sparsity-Aware Caches to Accelerate Deep Neural Networks. DATE 2020: 85-90 - [c199]Manik Singhal, Vijay Raghunathan, Anand Raghunathan:
Communication-efficient View-Pooling for Distributed Multi-View Neural Networks. DATE 2020: 1390-1395 - [c198]David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin:
Emerging Neural Workloads and Their Impact on Hardware. DATE 2020: 1462-1471 - [c197]Sanchari Sen, Balaraman Ravindran, Anand Raghunathan:
EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness Against Adversarial Attacks. ICLR 2020 - [c196]Vinod Ganesan, Surya Selvam, Sanchari Sen, Pratyush Kumar, Anand Raghunathan:
A Case for Generalizable DNN Cost Models for Mobile Devices. IISWC 2020: 169-180 - [c195]Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan:
Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks. IJCNN 2020: 1-7 - [i19]Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy:
Gradual Channel Pruning while Training using Feature Relevance Scores for Convolutional Neural Networks. CoRR abs/2002.09958 (2020) - [i18]Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan:
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. CoRR abs/2002.11151 (2020) - [i17]Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan:
Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks. CoRR abs/2003.02800 (2020) - [i16]Sanchari Sen, Balaraman Ravindran, Anand Raghunathan:
EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness against Adversarial Attacks. CoRR abs/2004.10162 (2020) - [i15]Sarada Krithivasan, Sanchari Sen, Anand Raghunathan:
Adversarial Sparsity Attacks on Deep Neural Networks. CoRR abs/2006.08020 (2020) - [i14]Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan:
Optimizing Transformers with Approximate Computing for Faster, Smaller and more Accurate NLP Models. CoRR abs/2010.03688 (2020) - [i13]Reena Elangovan, Shubham Jain, Anand Raghunathan:
Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration. CoRR abs/2011.13000 (2020)
2010 – 2019
- 2019
- [j100]Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried Haensch, Kaushik Roy, Anand Raghunathan:
Neural network accelerator design with resistive crossbars: Opportunities and challenges. IBM J. Res. Dev. 63(6): 10:1-10:13 (2019) - [j99]Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks. IEEE Trans. Computers 68(6): 912-925 (2019) - [c194]Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan:
Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing. COMAD/CODS 2019: 150-156 - [c193]Ashish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das, Bharat Kaul, Anand Raghunathan:
X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks. DAC 2019: 130 - [c192]Younghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan:
Data Subsetting: A Data-Centric Approach to Approximate Computing. DATE 2019: 576-581 - [c191]Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks. ISLPED 2019: 1-6 - [c190]Sandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta:
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation. ISLPED 2019: 1-6 - [c189]Jacob R. Stevens, Ashish Ranjan, Dipankar Das, Bharat Kaul, Anand Raghunathan:
Manna: An Accelerator for Memory-Augmented Neural Networks. MICRO 2019: 794-806 - [p2]Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan:
Automatic Synthesis Techniques for Approximate Circuits. Approximate Circuits 2019: 123-140 - [i12]Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
TiM-DNN: Ternary in-Memory accelerator for Deep Neural Networks. CoRR abs/1909.06892 (2019) - [i11]Sandeep Krishna Thirumala, Yi-Tse Hung, Shubham Jain, Arnab Raha, Niharika Thakuria, Vijay Raghunathan, Anand Raghunathan, Zhihong Chen, Sumeet Kumar Gupta:
Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support. CoRR abs/1912.07821 (2019) - 2018
- [j98]Sybille Hellebrand, Jörg Henkel, Anand Raghunathan, Hans-Joachim Wunderlich:
Guest Editors' Introduction. IEEE Embed. Syst. Lett. 10(1): 1 (2018) - [j97]Setareh Behroozi, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim:
A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensory Data Transfer. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 379-390 (2018) - [j96]Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Bing Han, Parami Wijesinghe, Akhilesh Jaiswal, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy:
Energy Efficient Neural Computing: A Study of Cross-Layer Approximations. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 796-809 (2018) - [j95]Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy:
Energy-Efficient Neural Computing with Approximate Multipliers. ACM J. Emerg. Technol. Comput. Syst. 14(2): 16:1-16:23 (2018) - [j94]Sanchari Sen, Anand Raghunathan:
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2266-2276 (2018) - [j93]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 470-483 (2018) - [c188]Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan:
ACCLIB: Accelerators as libraries. DATE 2018: 245-248 - [c187]Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan:
Computing-in-memory with spintronics. DATE 2018: 1640-1645 - [c186]Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan:
AxBA: an approximate bus architecture framework. ICCAD 2018: 43 - [c185]Kyuin Lee, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim:
SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones. ICCD 2018: 234-241 - [i10]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars. CoRR abs/1809.00072 (2018) - [i9]Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan:
Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing. CoRR abs/1809.01701 (2018) - 2017
- [j92]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
CABA: Continuous Authentication Based on BioAura. IEEE Trans. Computers 66(5): 759-772 (2017) - [j91]Younghyun Kim, Vijay Raghunathan, Anand Raghunathan:
Design and Management of Battery-Supercapacitor Hybrid Electrical Energy Storage Systems for Regulation Services. IEEE Trans. Multi Scale Comput. Syst. 3(1): 12-24 (2017) - [j90]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Wearable Medical Sensor-Based System Design: A Survey. IEEE Trans. Multi Scale Comput. Syst. 3(2): 124-138 (2017) - [j89]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. IEEE Trans. Multi Scale Comput. Syst. 3(4): 255-268 (2017) - [j88]Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan:
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 462-475 (2017) - [j87]Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti:
Approximate Error Detection With Stochastic Checkers. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2258-2270 (2017) - [j86]Priyadarshini Panda, Swagath Venkataramani, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy:
Energy-Efficient Object Detection Using Semantic Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2673-2677 (2017) - [c184]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - [c183]Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
Approximate computing for spiking neural networks. DATE 2017: 193-198 - [c182]Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan:
STAxCache: An approximate, energy efficient STT-MRAM cache. DATE 2017: 356-361 - [c181]Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan:
ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. ISCA 2017: 13-26 - [c180]Younghyun Kim, Setareh Behroozi, Vijay Raghunathan, Anand Raghunathan:
AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing. ISLPED 2017: 1-6 - [c179]Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan:
Approximate memory compression for energy-efficiency. ISLPED 2017: 1-6 - [c178]Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, Anand Raghunathan:
A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks. ISLPED 2017: 1-6 - [c177]Amit Sabne, Xiao Wang, Sherman J. Kisner, Charles A. Bouman, Anand Raghunathan, Samuel P. Midkiff:
Model-based Iterative CT Image Reconstruction on GPUs. PPoPP 2017: 207-220 - [i8]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory with Spin-Transfer Torque Magnetic RAM. CoRR abs/1703.02118 (2017) - [i7]Sanjay Ganapathy, Swagath Venkataramani, Balaraman Ravindran, Anand Raghunathan:
DyVEDeep: Dynamic Variable Effort Deep Neural Networks. CoRR abs/1704.01137 (2017) - [i6]Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks. CoRR abs/1711.06315 (2017) - 2016
- [j85]Kaushik Roy, Byunghoo Jung, Dimitrios Peroulis, Anand Raghunathan:
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. IEEE Des. Test 33(3): 56-65 (2016) - [j84]Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC. ACM J. Emerg. Technol. Comput. Syst. 13(2): 20:1-20:20 (2016) - [j83]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. 13(2): 23:1-23:22 (2016) - [j82]Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE 104(7): 1449-1488 (2016) - [j81]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65(4): 1010-1024 (2016) - [j80]Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 1-22 (2016) - [j79]Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Physiological Information Leakage: A New Frontier in Health Information Security. IEEE Trans. Emerg. Top. Comput. 4(3): 321-334 (2016) - [j78]Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy:
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 992-1002 (2016) - [j77]Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Yun Pan, Charles A. Bouman, Anand Raghunathan:
EMBIRA: An Accelerator for Model-Based Iterative Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3243-3256 (2016) - [j76]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
Emulation-Based Analysis of System-on-Chip Performance Under Variations. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3401-3414 (2016) - [c176]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Efficient embedded learning for IoT devices. ASP-DAC 2016: 308-311 - [c175]Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Designing approximate circuits using clock overgating. DAC 2016: 15:1-15:6 - [c174]Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. DAC 2016: 98:1-98:6 - [c173]Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. DATE 2016: 145-150 - [c172]Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
Approximation through logic isolation for the design of quality configurable circuits. DATE 2016: 612-617 - [c171]Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti:
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. ISLPED 2016: 266-271 - [c170]Xiao Wang, Amit Sabne, Sherman J. Kisner, Anand Raghunathan, Charles A. Bouman, Samuel P. Midkiff:
High performance model based image reconstruction. PPoPP 2016: 2:1-2:12 - [c169]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Approximate Computing. VLSID 2016: 3-4 - [c168]Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy:
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. VLSID 2016: 32-37 - [i5]Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing. CoRR abs/1602.08557 (2016) - 2015
- [j75]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. 12(1): 4:1-4:27 (2015) - [j74]Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy:
Exploring Spin-Transfer-Torque Devices for Logic Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1441-1454 (2015) - [j73]Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. IEEE J. Biomed. Health Informatics 19(6): 1893-1905 (2015) - [j72]Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Energy-Efficient Long-term Continuous Personal Health Monitoring. IEEE Trans. Multi Scale Comput. Syst. 1(2): 85-98 (2015) - [j71]Ali Mirtar, Sujit Dey, Anand Raghunathan:
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding. ACM Trans. Design Autom. Electr. Syst. 20(4): 50:1-50:27 (2015) - [j70]Ali Mirtar, Sujit Dey, Anand Raghunathan:
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1017-1030 (2015) - [c167]Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan:
Vibration-based secure side channel for medical devices. DAC 2015: 32:1-32:6 - [c166]Swagath Venkataramani, Anand Raghunathan, Jie Liu, Mohammed Shoaib:
Scalable-effort classifiers for energy-efficient machine learning. DAC 2015: 67:1-67:6 - [c165]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing and the quest for computing efficiency. DAC 2015: 120:1-120:6 - [c164]Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Approximate storage for energy efficient spintronic memories. DAC 2015: 195:1-195:6 - [c163]Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan:
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. DATE 2015: 181-186 - [c162]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE 2015: 659-664 - [c161]Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan:
Quality configurable reduce-and-rank for energy efficient approximate computing. DATE 2015: 665-670 - [c160]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Computing approximately, and efficiently. DATE 2015: 748-751 - [c159]Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. DATE 2015: 1575-1578 - [c158]Kaushik Roy, Anand Raghunathan:
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications. ISVLSI 2015: 473-475 - [i4]Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC. CoRR abs/1509.08806 (2015) - [i3]Priyadarshini Panda, Abhronil Sengupta, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing. CoRR abs/1509.08970 (2015) - 2014
- [j69]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
A defense framework against malware and vulnerability exploits. Int. J. Inf. Sec. 13(5): 439-452 (2014) - [j68]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Trustworthiness of Medical Devices and Body Area Networks. Proc. IEEE 102(8): 1174-1188 (2014) - [j67]Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Scalable Effort Hardware Design. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2004-2016 (2014) - [c157]Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan:
Variation Aware Cache Partitioning for Multithreaded Programs. DAC 2014: 199:1-199:6 - [c156]Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
ASLAN: Synthesis of approximate sequential circuits. DATE 2014: 1-6 - [c155]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing for efficient information processing. ESTIMedia 2014: 9-10 - [c154]Younghyun Kim, Vijay Raghunathan, Anand Raghunathan:
Design and management of hybrid electrical energy storage systems for regulation services. IGCC 2014: 1-9 - [c153]Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA 2014: 253-264 - [c152]Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED 2014: 15-20 - [c151]Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
AxNN: energy-efficient neuromorphic systems using approximate computing. ISLPED 2014: 27-32 - [c150]Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
StoRM: a stochastic recognition and mining processor. ISLPED 2014: 39-44 - [c149]Vivek Joy Kozhikkottu, Swagath Venkataramani, Sujit Dey, Anand Raghunathan:
Variation tolerant design of a vector processor for recognition, mining and synthesis. ISLPED 2014: 239-244 - [c148]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar:
ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters. USENIX ATC 2014: 1-12 - [e3]Karam S. Chatha, Rolf Ernst, Anand Raghunathan, Ravishankar R. Iyer:
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014. ACM 2014, ISBN 978-1-4503-3050-3 [contents] - [i2]Deliang Fan, Yong Shim, Anand Raghunathan, Kaushik Roy:
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks. CoRR abs/1412.8648 (2014) - 2013
- [j66]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods. IEEE Embed. Syst. Lett. 5(3): 50-53 (2013) - [j65]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection. IEEE Trans. Biomed. Circuits Syst. 7(6): 871-881 (2013) - [j64]Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy:
Low-Power Digital Signal Processing Using Approximate Adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 124-137 (2013) - [j63]Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling. ACM Trans. Embed. Comput. Syst. 12(2s): 90:1-90:23 (2013) - [c147]Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing: An integrated hardware approach. ACSSC 2013: 111-117 - [c146]Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan:
Energy-efficient recognition and mining processor using scalable effort design. CICC 2013: 1-4 - [c145]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Towards trustworthy medical devices and body area networks. DAC 2013: 14:1-14:6 - [c144]Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan:
Relax-and-retime: a methodology for energy-efficient recovery based design. DAC 2013: 111:1-111:6 - [c143]Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Analysis and characterization of inherent application resilience for approximate computing. DAC 2013: 113:1-113:9 - [c142]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. DATE 2013: 1367-1372 - [c141]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE 2013: 1825-1830 - [c140]Anand Raghunathan, Kaushik Roy:
Approximate computing: Energy-efficient computing with good-enough results. IOLTS 2013: 258 - [c139]Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED 2013: 64-69 - [c138]Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Quality programmable vector processors for approximate computing. MICRO 2013: 1-12 - [c137]Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Reading spin-torque memory with spin-torque sensors. NANOARCH 2013: 40-41 - [c136]Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan:
Localized Heating for Building Energy Efficiency. VLSI Design 2013: 13-18 - [c135]Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha:
Energy-efficient and Secure Sensor Data Transmission Using Encompression. VLSI Design 2013: 31-36 - [c134]Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Emerging Frontiers in Embedded Security. VLSI Design 2013: 203-208 - 2012
- [j62]Yuvraj Agarwal, Anand Raghunathan:
Guest Editors' Introduction: Green Buildings. IEEE Des. Test Comput. 29(4): 5-7 (2012) - [j61]Chunxiao Li, Niraj K. Jha, Anand Raghunathan:
Secure reconfiguration of software-defined radio. ACM Trans. Embed. Comput. Syst. 11(1): 10:1-10:22 (2012) - [j60]Divya Arora, Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment. ACM Trans. Embed. Comput. Syst. 11(3): 60:1-60:20 (2012) - [j59]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
A Trusted Virtual Machine in an Untrusted Management Environment. IEEE Trans. Serv. Comput. 5(4): 472-483 (2012) - [j58]W. Paul Griffin, Anand Raghunathan, Kaushik Roy:
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 791-803 (2012) - [j57]Saumya Chandra, Anand Raghunathan, Sujit Dey:
Variation-Aware Voltage Level Selection. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 925-936 (2012) - [c133]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar:
Tarazu: optimizing MapReduce on heterogeneous clusters. ASPLOS 2012: 61-74 - [c132]Reza Farivar, Anand Raghunathan, Srimat T. Chakradhar, Harshit Kharbanda, Roy H. Campbell:
PIC: Partitioned Iterative Convergence for Clusters. CLUSTER 2012: 391-401 - [c131]Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy:
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. DAC 2012: 492-497 - [c130]Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan:
SALSA: systematic logic synthesis of approximate circuits. DAC 2012: 796-801 - [c129]Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan:
Recovery-based design for variation-tolerant SoCs. DAC 2012: 826-833 - [c128]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436 - [c127]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. ETS 2012: 1 - [c126]Ali Mirtar, Sujit Dey, Anand Raghunathan:
Adaptation of video encoding to address dynamic thermal management effects. IGCC 2012: 1-10 - [c125]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED 2012: 185-190 - [c124]Jacques A. Pienaar, Srimat T. Chakradhar, Anand Raghunathan:
Automatic generation of software pipelines for heterogeneous parallel systems. SC 2012: 24 - 2011
- [j56]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
A framework for defending embedded systems against software attacks. ACM Trans. Embed. Comput. Syst. 10(3): 33:1-33:23 (2011) - [c123]Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608 - [c122]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
VESPA: Variability emulation for System-on-Chip performance analysis. DATE 2011: 2-7 - [c121]Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy:
Design of voltage-scalable meta-functions for approximate computing. DATE 2011: 950-955 - [c120]Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan:
MACACO: Modeling and analysis of circuits for approximate computing. ICCAD 2011: 667-673 - [c119]Jacques A. Pienaar, Anand Raghunathan, Srimat T. Chakradhar:
MDR: performance model driven runtime for heterogeneous parallel platforms. ICS 2011: 225-234 - [c118]Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy:
IMPACT: imprecise adders for low-power approximate computing. ISLPED 2011: 409-414 - [c117]Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan:
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH 2011: 122-128 - 2010
- [j55]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Aware System-Level Power Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1173-1184 (2010) - [c116]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
A Secure User Interface for Web Applications Running Under an Untrusted Operating System. CIT 2010: 865-870 - [c115]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
Secure Virtual Machine Execution under an Untrusted Management OS. IEEE CLOUD 2010: 172-179 - [c114]Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi:
Best-effort semantic document search on GPUs. GPGPU 2010: 86-93 - [c113]Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560 - [c112]Srimat T. Chakradhar, Anand Raghunathan:
Best-effort computing: re-thinking parallel software and hardware. DAC 2010: 865-870 - [c111]Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Surendra Byna:
Exploiting the forgiving nature of applications for scalable parallel execution. IPDPS 2010: 1-12 - [c110]Kaushik Roy, Byunghoo Jung, Anand Raghunathan:
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. VLSI Design 2010: 464-469 - [c109]Swarup Bhunia, Anand Raghunathan:
Special session 11B: Hot topic hardware security: Design, test and verification issues. VTS 2010: 349
2000 – 2009
- 2009
- [j54]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Tolerant Dynamic Power Management at the System-Level. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1220-1232 (2009) - [c108]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
An architecture for secure software defined radio. DATE 2009: 448-453 - [c107]Jiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan:
Best-effort parallel execution framework for Recognition and mining applications. IPDPS 2009: 1-12 - [c106]Narayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar:
A framework for efficient and scalable execution of domain-specific templates on GPUs. IPDPS 2009: 1-12 - [c105]Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy:
Coping with Variations through System-Level Design. VLSI Design 2009: 581-586 - 2008
- [j53]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
Analysis and design of a hardware/software trusted platform module for embedded systems. ACM Trans. Embed. Comput. Syst. 8(1): 8:1-8:31 (2008) - [j52]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1413-1426 (2008) - [j51]Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1441-1453 (2008) - [c104]Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar:
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. DATE 2008: 1148-1153 - [c103]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
Dynamic Binary Instrumentation-Based Framework for Malware Defense. DIMVA 2008: 64-87 - 2007
- [j50]Patrick Schaumont, Anand Raghunathan:
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design. IEEE Des. Test Comput. 24(6): 518-520 (2007) - [j49]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 542-552 (2007) - [j48]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1843-1854 (2007) - [j47]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2035-2045 (2007) - [j46]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. 7(1): 2:1-2:26 (2007) - [j45]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 296-308 (2007) - [j44]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 465-470 (2007) - [j43]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 546-559 (2007) - [j42]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 605-609 (2007) - [j41]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 699-710 (2007) - [j40]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1191-1204 (2007) - [c102]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations. DAC 2007: 877-882 - [c101]Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan:
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. DAC 2007: 883-886 - [c100]Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Energy and execution time analysis of a software-based trusted platform module. DATE 2007: 1128-1133 - [c99]Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan:
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. VLSI Design 2007: 513-520 - [e2]Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan:
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007. ACM 2007, ISBN 978-1-59593-709-4 [contents] - [i1]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Hardware Accelerated Power Estimation. CoRR abs/0710.4742 (2007) - 2006
- [j39]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1589-1602 (2006) - [j38]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1969-1989 (2006) - [j37]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2103-2117 (2006) - [j36]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2193-2206 (2006) - [j35]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) - [j34]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana:
The LOTTERYBUS on-chip communication architecture. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 596-608 (2006) - [j33]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1175-1188 (2006) - [j32]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1295-1308 (2006) - [c98]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Architectural support for safe software execution on embedded processors. CODES+ISSS 2006: 106-111 - [c97]Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
Systematic software-based self-test for pipelined processors. DAC 2006: 393-398 - [c96]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501 - [c95]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6 - [c94]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum 2006: 18-23 - [c93]Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan:
Adaptive data placement in an embedded multiprocessor thread library. DATE 2006: 698-699 - [c92]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE 2006: 728-733 - [c91]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Active Learning Driven Data Acquisition for Sensor Networks. ISCC 2006: 929-934 - [c90]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Considering process variations during system-level power analysis. ISLPED 2006: 342-345 - [c89]Gang Tan, Andrew W. Appel, Srimat Chakradhar, Anand Raghunathan, Srivaths Ravi, Daniel C. Wang:
Safe Java Native Interface. ISSSE 2006 - [c88]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design 2006: 299-304 - [c87]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476 - [e1]Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu:
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006. ACM 2006, ISBN 1-59593-462-6 [contents] - 2005
- [j31]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1677-1693 (2005) - [j30]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1694-1711 (2005) - [j29]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Energy macromodeling of embedded operating systems. ACM Trans. Embed. Comput. Syst. 4(1): 231-254 (2005) - [c86]Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
SECA: security-enhanced communication architecture. CASES 2005: 78-89 - [c85]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC 2005: 239-242 - [c84]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195 - [c83]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid simulation for embedded software energy estimation. DAC 2005: 23-26 - [c82]Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247 - [c81]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC 2005: 571-574 - [c80]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Power emulation: a new paradigm for power estimation. DAC 2005: 700-705 - [c79]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE 2005: 178-183 - [c78]Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Hardware Accelerated Power Estimation. DATE 2005: 528-529 - [c77]Chulsung Park, Kanishka Lahiri, Anand Raghunathan:
Battery discharge characteristics of wireless sensor nodes: an experimental analysis. SECON 2005: 430-440 - [c76]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 - [c75]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556 - [c74]Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585 - 2004
- [j28]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 33-49 (2004) - [j27]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 216-228 (2004) - [j26]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 620-636 (2004) - [j25]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 652-664 (2004) - [j24]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient power profiling for battery-driven embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 919-932 (2004) - [j23]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Design space exploration for optimizing on-chip communication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 952-961 (2004) - [j22]Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1010-1019 (2004) - [j21]Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady:
Security in embedded systems: Design challenges. ACM Trans. Embed. Comput. Syst. 3(3): 461-491 (2004) - [j20]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 590-602 (2004) - [c73]Kanishka Lahiri, Anand Raghunathan:
Power analysis of system-level on-chip communication architectures. CODES+ISSS 2004: 236-241 - [c72]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. ESA/VLSI 2004: 601-605 - [c71]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated energy/performance macromodeling of embedded software. DAC 2004: 99-102 - [c70]Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan:
Security as a new dimension in embedded system design. DAC 2004: 753-760 - [c69]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Power estimation for cycle-accurate functional descriptions of hardware. ICCAD 2004: 668-675 - [c68]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis using computation-unit integrated memories. ICCAD 2004: 783-790 - [c67]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design 2004: 261-266 - [c66]Weidong Wang, Anand Raghunathan, Niraj K. Jha:
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. VLSI Design 2004: 267- - [c65]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605- - 2003
- [j19]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 615-627 (2003) - [j18]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
A simulation framework for energy-consumption analysis of OS-driven embedded applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1284-1294 (2003) - [j17]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 538-557 (2003) - [c64]Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey:
A scalable software-based self-test methodology for programmable processors. DAC 2003: 548-553 - [c63]Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater:
Securing Mobile Appliances: New Challenges for the System Designer. DATE 2003: 10176-10183 - [c62]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy Estimation for Extensible Processors. DATE 2003: 10682-10687 - [c61]Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. DATE 2003: 10706-10713 - [c60]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Software Architectural Transformations: A New Approach to Low Energy Embedded Software. DATE 2003: 11046-11051 - [c59]Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha:
A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI 2003: 11-14 - [c58]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD 2003: 46-53 - [c57]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290 - [c56]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Analyzing the energy consumption of security protocols. ISLPED 2003: 30-35 - [c55]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270 - [c54]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439 - [c53]Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design 2003: 467-473 - [p1]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Software Architectural Transformations. Embedded Software for SoC 2003: 467-484 - 2002
- [j16]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication-Based Power Management. IEEE Des. Test Comput. 19(4): 118-130 (2002) - [j15]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1037-1050 (2002) - [j14]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
Cosimulation-based power estimation for system-on-chip design. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 253-266 (2002) - [c52]Jacob Chang, Srivaths Ravi, Anand Raghunathan:
FLEXBAR: A crossbar switching fabric with improved performance and utilization. CICC 2002: 405-408 - [c51]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast system-level power profiling for battery-efficient system design. CODES 2002: 157-162 - [c50]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication architecture based power management for battery efficient system design. DAC 2002: 691-696 - [c49]Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass:
System design methodologies for a wireless security processing platform. DAC 2002: 777-782 - [c48]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Battery-efficient architecture for an 802.11 MAC processor. ICC 2002: 669-674 - [c47]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Optimizing public-key encryption for wireless clients. ICC 2002: 1050-1056 - [c46]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures. ICCAD 2002: 564-571 - [c45]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648 - [c44]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Embedded Operating System Energy Analysis and Macro-Modeling. ICCD 2002: 515-520 - [c43]Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi:
Securing Wireless Data: System Architecture Challenges. ISSS 2002: 195-200 - [c42]Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. ASP-DAC/VLSI Design 2002: 261-267 - [c41]Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac:
High-Level Synthesis with SIMD Units. ASP-DAC/VLSI Design 2002: 407-413 - [c40]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Embedded Software Synthesis. ASP-DAC/VLSI Design 2002: 711-718 - [c39]J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski:
Innovations in Test Automation. VTS 2002: 43-46 - 2001
- [j13]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 768-783 (2001) - [c38]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana:
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001: 15-20 - [c37]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level Software Energy Macro-modeling. DAC 2001: 605-610 - [c36]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743 - [c35]Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552 - [c34]Anand Raghunathan, Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. VLSI Design 2001: 9-10 - [c33]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35 - [c32]Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63 - [c31]Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241 - 2000
- [j12]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000) - [j11]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 308-324 (2000) - [c30]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Power analysis of embedded operating systems. DAC 2000: 312-315 - [c29]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518 - [c28]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE 2000: 27-34 - [c27]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD 2000: 424-430 - [c26]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design 2000: 530-537
1990 – 1999
- 1999
- [j10]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 357-370 (1999) - [j9]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1114-1131 (1999) - [j8]Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1496-1508 (1999) - [j7]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 7-15 (1999) - [c25]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61 - [c24]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD 1999: 566-573 - [c23]Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466 - [c22]Kaushik Roy, Anand Raghunathan, Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609 - 1998
- [b1]Anand Raghunathan, Niraj K. Jha, Sujit Dey:
High-Level Power Analysis and Optimization. Kluwer 1998, ISBN 978-0-7923-8073-3, pp. I-XVI, 1-157 - [j6]Sujit Dey, Anand Raghunathan, Kenneth D. Wagner:
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. J. Electron. Test. 13(2): 79-91 (1998) - [j5]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 706-723 (1998) - [c21]Sujit Dey, Anand Raghunathan, Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC 1998: 205-210 - [c20]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES 1998: 117-121 - [c19]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113 - [c18]Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524 - [c17]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664 - [c16]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19 - 1997
- [j4]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1001-1014 (1997) - [j3]Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction in sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1157-1172 (1997) - [j2]Anand Raghunathan, Niraj K. Jha:
SCALP: an iterative-improvement-based low-power data path synthesis system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1260-1277 (1997) - [c15]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434 - [c14]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539 - 1996
- [c13]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Glitch Analysis and Reduction in Register Transfer Level. DAC 1996: 331-336 - [c12]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345 - [c11]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption. ICCAD 1996: 158-165 - [c10]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336 - [c9]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304 - [c8]Anand Raghunathan, Srimat T. Chakradhar:
Dynamic test Sequence compaction for Sequential Circuits. VLSI Design 1996: 170-173 - 1995
- [j1]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1408-1414 (1995) - [c7]Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104 - [c6]Anand Raghunathan, Srimat T. Chakradhar:
Acceleration techniques for dynamic vector compaction. ICCAD 1995: 310-317 - [c5]Anand Raghunathan, Niraj K. Jha:
An iterative improvement algorithm for low power data path synthesis. ICCAD 1995: 597-602 - [c4]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179 - [c3]Anand Raghunathan, Niraj K. Jha:
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. ISCAS 1995: 1069-1073 - [c2]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109 - 1994
- [c1]Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis for low Power. ICCD 1994: 318-322
Coauthor Index
Srimat T. Chakradhar
aka: Srimat Chakradhar
aka: Srimat Chakradhar
Vinay K. Chippa
aka: Vinay Kumar Chippa
aka: Vinay Kumar Chippa
[c216] [j114] [c206] [j76] [j71] [j70] [c157] [c149] [j57] [c129] [c126] [c122] [j55] [j54] [c105] [j52] [c102] [c92] [c90] [c81] [j28] [j26] [j24] [j23] [j22] [j17] [c64] [c53] [j16] [j14] [c51] [c50] [c48] [c42] [j13] [c34] [c33] [c32] [c29] [c28] [c27] [c26] [j9] [j8] [j7] [c25] [c24] [c22] [b1] [j6] [c21] [c20] [c17] [c16] [c15] [c13] [c11] [c9]
[i23] [j92] [j90] [j89] [j79] [j73] [j72] [c167] [j69] [j68] [j66] [j65] [c145] [c136] [c135] [c134] [j61] [j60] [j59] [j56] [c116] [c115] [c108] [j53] [c103] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [c100] [j39] [j38] [j37] [j36] [j35] [j33] [j32] [c98] [c96] [c95] [c94] [c91] [c88] [c87] [j31] [j30] [j29] [c85] [c84] [c83] [c82] [c79] [c76] [c75] [j28] [j27] [j25] [j22] [j20] [c72] [c71] [c69] [c68] [c67] [c66] [j19] [j18] [j17] [c62] [c60] [c59] [c58] [c57] [c56] [c53] [p1] [j15] [c46] [c45] [c44] [c40] [c37] [c36] [j12] [j11] [c30] [j10] [j9] [j8] [j7] [c25] [b1] [j5] [c19] [c17] [c16] [j4] [j2] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c5] [c4] [c3] [c1]
[j51] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [c100] [i1] [j39] [j38] [j37] [j36] [j35] [j33] [j32] [c98] [c97] [c96] [c95] [c94] [c91] [c89] [c88] [c87] [j30] [c86] [c85] [c84] [c83] [c82] [c80] [c79] [c78] [c76] [c75] [j27] [j25] [j21] [c71] [c70] [c69] [c68] [c67] [c65] [c64] [c63] [c62] [c61] [c58] [c57] [c56] [c55] [c54] [c52] [c49] [c47] [c46] [c45] [c43] [c35]
[i34] [c219] [i33] [i31] [j115] [i30] [j112] [c214] [c213] [p3] [i25] [j110] [j108] [j107] [j106] [i19] [j100] [p2] [j96] [j95] [j93] [c187] [i10] [j86] [c184] [c182] [i8] [j85] [j84] [j83] [j82] [j81] [j80] [j78] [c176] [c175] [c174] [c173] [c169] [c168] [i5] [j75] [j74] [c165] [c164] [c163] [c162] [c160] [c159] [c158] [i4] [i3] [j67] [c156] [c155] [c153] [c152] [c151] [c150] [i2] [j64] [j63] [c147] [c146] [c143] [c142] [c141] [c140] [c139] [c138] [c137] [j58] [c131] [c130] [c128] [c127] [c125] [c123] [c121] [c120] [c118] [c117] [c113] [c110] [c105] [c22]
[j120] [c212] [i24] [c203] [c202] [j106] [j103] [j99] [c192] [c191] [p2] [j95] [j88] [j87] [j86] [c183] [c182] [c181] [c178] [i7] [i6] [j77] [c176] [c175] [c174] [c173] [c172] [c171] [c169] [i5] [j74] [c166] [c165] [c164] [c161] [c160] [c159] [i3] [c156] [c155] [c153] [c151] [c150] [c149] [c147] [c144] [c142] [c138] [c130]
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