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ORCIDMasanori Hashimoto
Person information
- affiliation: Kyoto University, Sakyo, Japan
- affiliation: Osaka University, Suita, Japan
- affiliation (PhD 2001): Kyoto University, Sakyo, Japan
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Journal Articles
- 2023
[j96]Ángel López García-Arias
, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access 11: 16588-16604 (2023)- [j95]Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto:
Vulnerability Estimation of DNN Model Parameters with Few Fault Injections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 523-531 (2023) - [j94]Hiromitsu Awano, Masanori Hashimoto:
B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA. Integr. 89: 1-8 (2023) - [j93]Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu, Masanori Hashimoto:
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3978-3991 (2023) - [j92]Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu:
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2246-2250 (2023) - 2022
- [j91]TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto:
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 497-508 (2022) - [j90]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 509-517 (2022) - [j89]Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano:
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. 105-D(7): 1273-1282 (2022) - [j88]Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada:
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits 57(7): 2250-2262 (2022) - [j87]Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann:
VirtualSync+: Timing Optimization With Virtual Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5526-5540 (2022) - 2021
- [j86]Ryo Shirai, Yuichi Itoh, Masanori Hashimoto:
Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers. IEEE Access 9: 26616-26632 (2021) - 2020
- [j85]Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto:
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1447-1455 (2020) - [j84]TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto:
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training. Integr. 74: 19-31 (2020) - [j83]Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto:
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2572-2587 (2020) - 2019
- [j82]Liao Wang, Masanori Hashimoto:
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate. IEICE Trans. Electron. 102-C(4): 296-302 (2019) - [j81]Yutaka Masuda, Masanori Hashimoto:
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 867-877 (2019) - [j80]Takahiro Nakayama, Masanori Hashimoto:
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 914-917 (2019) - [j79]Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe:
Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. 69: 161-179 (2019) - [j78]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - 2018
- [j77]Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j76]Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto:
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(9): 1298-1307 (2018) - [j75]Ryutaro Doi, Masanori Hashimoto, Takao Onoye:
An analytic evaluation on soft error immunity enhancement due to temporal triplication. Int. J. Embed. Syst. 10(1): 22-31 (2018) - [j74]Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [j73]Yutaka Masuda, Takao Onoye, Masanori Hashimoto:
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2217-2229 (2018) - [j72]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - 2017
- [j71]Yutaka Masuda, Takao Onoye, Masanori Hashimoto:
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1452-1463 (2017) - [j70]Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin:
Minimizing detection-to-boosting latency toward low-power error-resilient circuits. Integr. 58: 236-244 (2017) - [j69]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - 2015
- [j68]Daisuke Fukuda, Kenichi Watanabe, Yuji Kanazawa, Masanori Hashimoto:
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1467-1474 (2015) - [j67]Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye:
Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2607-2613 (2015) - 2014
- [j66]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1461-1467 (2014) - [j65]Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1468-1482 (2014) - [j64]Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1483-1491 (2014) - [j63]Daisuke Fukuda, Kenichi Watanabe, Naoki Idani, Yuji Kanazawa, Masanori Hashimoto:
Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2373-2382 (2014) - [j62]Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
A Process and Temperature Tolerant Oscillator-Based True Random Number Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2393-2399 (2014) - [j61]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - 2013
- [j60]Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye:
A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation. IEICE Electron. Express 10(4): 20130022 (2013) - [j59]Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. IEICE Electron. Express 10(5): 20130081 (2013) - [j58]Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye:
Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 459-468 (2013) - [j57]Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
Jitter Amplifier for Oscillator-Based True Random Number Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(3): 684-696 (2013) - [j56]Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. IEICE Trans. Inf. Syst. 96-D(8): 1624-1631 (2013) - [j55]Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations. Integr. 46(4): 345-358 (2013) - [j54]Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. IEEE Trans. Inf. Forensics Secur. 8(8): 1331-1342 (2013) - [j53]Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye:
Supply Noise Suppression by Triple-Well Structure. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 781-785 (2013) - [j52]Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2165-2178 (2013) - 2012
- [j51]Yasumichi Takai, Masanori Hashimoto, Takao Onoye:
Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2220-2225 (2012) - [j50]Takashi Enami, Takashi Sato, Masanori Hashimoto:
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2261-2271 (2012) - [j49]Shuta Kimura, Masanori Hashimoto, Takao Onoye:
A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2292-2300 (2012) - [j48]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 333-343 (2012) - 2011
- [j47]Takaaki Okumura, Masanori Hashimoto:
Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(10): 1948-1953 (2011) - [j46]Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
Extracting Device-Parameter Variations with RO-Based Sensors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2537-2544 (2011) - [j45]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2545-2553 (2011) - [j44]Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye:
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 299-303 (2011) - 2010
- [j43]Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto:
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. 93-C(3): 388-392 (2010) - [j42]Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
Prediction of Self-Heating in Short Intra-Block Wires. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(3): 583-594 (2010) - [j41]Takashi Enami, Shinyu Ninomiya, Kenichi Shinkai, Shinya Abe, Masanori Hashimoto:
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2399-2408 (2010) - [j40]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2417-2423 (2010) - [j39]Shinyu Ninomiya, Masanori Hashimoto:
Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2441-2446 (2010) - [j38]Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto:
Gate Delay Estimation in STA under Dynamic Power Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2447-2455 (2010) - [j37]Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 250-260 (2010) - [j36]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1118-1129 (2010) - 2009
- [j35]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. 92-C(2): 281-285 (2009) - [j34]Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 990-997 (2009) - [j33]Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto:
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3016-3023 (2009) - [j32]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3094-3102 (2009) - [j31]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform. IEEE J. Solid State Circuits 44(6): 1745-1755 (2009) - [j30]Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto:
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 541-553 (2009) - 2008
- [j29]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Trans. Inf. Syst. 91-D(3): 655-660 (2008) - [j28]Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto:
Impact of Well Edge Proximity Effect on Timing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3461-3464 (2008) - [j27]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3474-3480 (2008) - [j26]Shinya Abe, Masanori Hashimoto, Takao Onoye:
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3481-3487 (2008) - [j25]Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa:
Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3651-3662 (2008) - [j24]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects. IEEE J. Solid State Circuits 43(3): 718-728 (2008) - 2007
- [j23]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 724-731 (2007) - [j22]Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto:
Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 808-814 (2007) - [j21]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Trans. Electron. 90-C(6): 1267-1273 (2007) - [j20]Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera:
Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2661-2668 (2007) - [j19]Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa:
Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2712-2717 (2007) - [j18]Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye:
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 868-872 (2007) - 2006
- [j17]Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto:
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3491-3499 (2006) - [j16]Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa:
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3538-3545 (2006) - [j15]Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3560-3568 (2006) - [j14]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3585-3593 (2006) - [j13]Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto:
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3666-3670 (2006) - 2005
- [j12]Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera:
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Trans. Electron. 88-C(3): 437-444 (2005) - [j11]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 885-891 (2005) - [j10]Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3375-3381 (2005) - [j9]Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto:
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3382-3389 (2005) - [j8]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3429-3436 (2005) - [j7]Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3453-3462 (2005) - [j6]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of On-Chip Inductance on Power Distribution Grid. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3564-3572 (2005) - 2004
- [j5]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Equivalent waveform propagation for static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 498-508 (2004) - 2003
- [j4]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative Frequency for Interconnect R(f)L(f)C Extraction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2942-2951 (2003) - [j3]Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2965-2973 (2003) - [j2]Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3204-3207 (2003) - 2002
- [j1]Masanori Hashimoto, Hidetoshi Onodera:
Increase in Delay Uncertainty by Performance Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2799-2802 (2002)
Conference and Workshop Papers
- 2024
- [c142]Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto:
Logic Locking over TFHE for Securing User Data and Algorithms. ASPDAC 2024: 600-605 - [c141]Kozo Takeuchi, Takashi Kato, Masanori Hashimoto:
An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs. IRPS 2024: 1-4 - 2023
- [c140]Chinamu Kawano, Masanori Hashimoto:
Performance comparison of memristor crossbar-based analog and FPGA-based digital weight-memory-less neural networks. ICRC 2023: 1-5 - [c139]Riku Iwamoto, Masanori Hashimoto:
Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication. IOLTS 2023: 1-7 - [c138]Kazusa Takami, Yuibi Gomi, Shin-ichiro Abe, Wang Liao, Seiya Manabe, Tetsuro Matsumoto, Masanori Hashimoto:
Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons. IRPS 2023: 1-6 - [c137]Minoru Harimaya, Ryo Shirai, Masanori Hashimoto:
Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers. IUI Companion 2023: 130-133 - 2022
- [c136]Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto:
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections. DATE 2022: 60-63 - [c135]Ryo Shirai, Masanori Hashimoto:
Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs. IUI Companion 2022: 89-92 - [c134]Toshihisa Tanaka, Ryo Shirai, Masanori Hashimoto:
DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object. MWSCAS 2022: 1-4 - [c133]Masafumi Tanakal, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto:
Investigating Small Device Implementation of FRET-based Optical Reservoir Computing. MWSCAS 2022: 1-4 - 2021
- [c132]TaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto:
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization. ASP-DAC 2021: 284-290 - [c131]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC 2021: 205 - [c130]Dehua Liang, Masanori Hashimoto, Hiromitsu Awano:
BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. DATE 2021: 587-590 - [c129]Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi:
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE 2021: 838-843 - [c128]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE 2021: 1260-1265 - [c127]TaiYu Cheng, Masanori Hashimoto:
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling. ISCAS 2021: 1-5 - [c126]Ryo Shirai, Masanori Hashimoto:
Submarine LED: Wirelessly powered underwater display controlling its buoyancy. SIGGRAPH ASIA Posters 2021: 6:1-6:2 - 2020
- [c125]Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto:
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network. AICAS 2020: 251-255 - [c124]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo:
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. ASP-DAC 2020: 163-168 - [c123]Masanori Hashimoto, Wang Liao:
Soft Error and Its Countermeasures in Terrestrial Environment. ASP-DAC 2020: 617-622 - [c122]Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto:
Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. DATE 2020: 983-986 - [c121]Hiromitsu Awano, Masanori Hashimoto:
BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA. DATE 2020: 1402-1407 - [c120]Shin-ichiro Abe, Tatsuhiko Sato, Junya Kuroda, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Kojiro Ito, Masanori Hashimoto, Masahide Harada, Kenichi Oikawa, Yasuhiro Miyake:
Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets. IRPS 2020: 1-7 - [c119]Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto:
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS 2020: 1-5 - [c118]Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto:
Low-Cost Reservoir Computing using Cellular Automata and Random Forests. ISCAS 2020: 1-5 - [c117]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504 - [c116]Jun Chen, Masanori Hashimoto:
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. ITC 2020: 1-8 - [c115]Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto:
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. ITC 2020: 1-5 - [c114]Ryohei Shimizu, Ryo Shirai, Masanori Hashimoto:
Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis. MWSCAS 2020: 57-60 - 2019
- [c113]Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto:
Training Data Reduction using Support Vectors for Neural Networks. APSIPA 2019: 1405-1410 - [c112]Shota Fukui, Jaehoon Yu, Masanori Hashimoto:
Distilling Knowledge for Non-Neural Networks. APSIPA 2019: 1411-1416 - [c111]Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Keita Nakano, Hayato Takeshita, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake:
Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs. IRPS 2019: 1-5 - [c110]Pei Hao Chen, Ryo Shirai, Masanori Hashimoto:
Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes. IUI Companion 2019: 57-58 - [c109]TaiYu Cheng, Jaehoon Yu, Masanori Hashimoto:
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier. PATMOS 2019: 91-96 - 2018
- [c108]Yutaka Masuda, Masanori Hashimoto:
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC 2018: 159-165 - [c107]Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto:
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. A-SSCC 2018: 55-58 - [c106]Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC 2018: 26:1-26:6 - [c105]Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto:
Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD 2018: 39 - [c104]Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto:
Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD 2018: 68 - [c103]Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li:
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. ISQED 2018: 425-431 - [c102]Ryutaro Doi, Masanori Hashimoto:
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. ISVLSI 2018: 429-434 - [c101]Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu:
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI 2018: 522-527 - [c100]Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto:
A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes. NEWCAS 2018: 152-156 - [c99]Takahiro Nakayama, Masanori Hashimoto:
Hold violation analysis for functional test of ultra-low temperature circuits at room temperature. VLSI-DAT 2018: 1-4 - 2017
- [c98]Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose:
Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. ASICON 2017: 1065-1068 - [c97]Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto:
Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. ISCAS 2017: 1-4 - [c96]Kauzki Hirosue, Shohei Ukawa, Yuichi Itoh, Takao Onoye, Masanori Hashimoto:
GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction. IUI 2017: 173-178 - [c95]Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto:
Near-future traffic evaluation based navigation for automated driving vehicles. Intelligent Vehicles Symposium 2017: 1465-1470 - [c94]Liao Wang, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto:
Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -. NEWCAS 2017: 33-36 - 2016
- [c93]Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC 2016: 705-711 - [c92]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - [c91]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD 2016: 63 - [c90]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS 2016: 84-89 - [c89]Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto:
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. SLIP 2016: 2:1-2:6 - 2015
- [c88]Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
An oscillator-based true random number generator with process and temperature tolerance. ASP-DAC 2015: 4-5 - [c87]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - [c86]Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye:
Area efficient device-parameter estimation using sensitivity-configurable ring oscillator. ASP-DAC 2015: 731-736 - [c85]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD 2015: 315-322 - [c84]Miho Ueno, Masanori Hashimoto, Takao Onoye:
Real-time on-chip supply voltage sensor and its application to trace-based timing error localization. IOLTS 2015: 188-193 - [c83]Taiki Uemura, Masanori Hashimoto:
Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag. IRPS 2015: 1 - [c82]Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto:
Soft error immune latch design for 20 nm bulk CMOS. IRPS 2015: 4 - [c81]Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto:
Impact of package on neutron induced single event upset in 20 nm SRAM. IRPS 2015: 9 - [c80]Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Stochastic timing error rate estimation under process and temporal variations. ITC 2015: 1-10 - [c79]Shohei Ukawa, Tatsuya Shinada, Masanori Hashimoto, Yuichi Itoh, Takao Onoye:
3D node localization from node-to-node distance information using cross-entropy method. VR 2015: 303-304 - 2014
- [c78]Masanori Hashimoto:
Stochastic verification of run-time performance adaptation with field delay testing. APCCAS 2014: 751-754 - [c77]Masanori Hashimoto:
Opportunities and Verification Challenges of Run-Time Performance Adaptation. ATS 2014: 248-253 - 2013
- [c76]Masanori Hashimoto:
Soft error immunity of subthreshold SRAM. ASICON 2013: 1-4 - [c75]Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif:
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS 2013: 1-6 - [c74]Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye:
Stochastic error rate estimation for adaptive speed control with field delay testing. ICCAD 2013: 107-114 - [c73]Miho Ueno, Masanori Hashimoto, Takao Onoye:
Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures. IPDPS Workshops 2013: 301-305 - [c72]Tatsuya Shinada, Masanori Hashimoto, Takao Onoye:
Proximity distance estimation based on capacitive coupling between 1mm3 sensor nodes. NEWCAS 2013: 1-4 - [c71]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye:
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig 2013: 1-6 - 2012
- [c70]Shuta Kimura, Masanori Hashimoto, Takao Onoye:
Body bias clustering for low test-cost post-silicon tuning. ASP-DAC 2012: 283-289 - [c69]Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. FPL 2012: 615-618 - [c68]Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose:
Signal-dependent analog-to-digital converter based on MINIMAX sampling. ISOCC 2012: 120-123 - [c67]Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama:
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig 2012: 1-7 - 2011
- [c66]Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
Jitter amplifier for oscillator-based true random number generator. ASP-DAC 2011: 81-82 - [c65]Masanori Hashimoto:
Run-time adaptive performance compensation using on-chip sensors. ASP-DAC 2011: 285-290 - [c64]Kenichi Shinkai, Masanori Hashimoto:
Device-parameter estimation with on-chip variation sensors considering random variability. ASP-DAC 2011: 683-688 - [c63]Yasumichi Takai, Masanori Hashimoto, Takao Onoye:
Power gating implementation for noise mitigation with body-tied triple-well structure. CICC 2011: 1-4 - [c62]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL 2011: 189-194 - [c61]Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
An oscillator-based true random number generator with jitter amplifier. ISCAS 2011: 725-728 - [c60]Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS 2011: 152-161 - 2010
- [c59]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362 - [c58]Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto:
Gate delay estimation in STA under dynamic power supply noise. ASP-DAC 2010: 775-780 - [c57]Takaaki Okumura, Masanori Hashimoto:
Setup time, hold time and clock-to-Q delay computation under dynamic supply noise. CICC 2010: 1-4 - [c56]Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. ACM Great Lakes Symposium on VLSI 2010: 197-202 - [c55]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED 2010: 646-651 - [c54]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED 2010: 839-844 - [c53]Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA 2010: 107-121 - 2009
- [c52]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271 - [c51]Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng:
High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390 - [c50]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218 - [c49]Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye:
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192 - [c48]Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED 2009: 51-56 - [c47]Shingo Watanabe, Masanori Hashimoto, Toshinori Sato:
A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407 - [c46]Shinyu Ninomiya, Masanori Hashimoto:
Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy. SoCC 2009: 337-340 - 2008
- [c45]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC 2008: 107-108 - [c44]Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto:
High performance current-mode differential logic. ASP-DAC 2008: 720-725 - [c43]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390 - [c42]Takashi Enami, Masanori Hashimoto, Takashi Sato:
Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425 - [c41]Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng:
On-chip high performance signaling using passive compensation. ICCD 2008: 182-187 - [c40]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8 - [c39]Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto:
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. ISPD 2008: 160-167 - [c38]Shinya Abe, Masanori Hashimoto, Takao Onoye:
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ISQED 2008: 520-525 - 2007
- [c37]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect. CICC 2007: 783-786 - [c36]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. CICC 2007: 869-872 - [c35]Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto:
Impact of well edge proximity effect on timing. ESSCIRC 2007: 115-118 - [c34]Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
Future Prediction of Self-Heating in Short Intra-Block Wires. ISQED 2007: 660-665 - 2006
- [c33]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520 - [c32]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects. CICC 2006: 721-724 - [c31]Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye:
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. CICC 2006: 861-864 - [c30]Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye:
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53 - [c29]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD 2006: 70-75 - 2005
- [c28]Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera:
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC 2005: 9-10 - [c27]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728 - [c26]Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto:
On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077 - [c25]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081 - [c24]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101 - [c23]Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement and analysis of delay variation due to inductive coupling. CICC 2005: 305-308 - [c22]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Design guideline for resistive termination of on-chip high-speed interconnects. CICC 2005: 613-616 - [c21]Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa:
A design scheme for sampling switch in active matrix LCD. ECCTD 2005: 31-34 - [c20]Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa:
Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163 - [c19]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69 - [c18]Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED 2005: 402-407 - 2004
- [c17]Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera:
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC 2004: 545-546 - [c16]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696 - [c15]Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera:
Performance limitation of on-chip global interconnects for high-speed signaling. CICC 2004: 489-492 - [c14]Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera:
Timing analysis considering spatial power/ground level variation. ICCAD 2004: 814-820 - [c13]Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED 2004: 36-41 - 2003
- [c12]Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto:
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC 2003: 149-155 - [c11]Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. ASP-DAC 2003: 589-590 - [c10]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Equivalent Waveform Propagation for Static Timing Analysis. ICCAD 2003: 169-175 - [c9]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD 2003: 18-23 - 2002
- [c8]Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera:
Crosstalk noise optimization by post-layout transistor sizing. ISPD 2002: 126-130 - [c7]Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287 - 2001
- [c6]Masanori Hashimoto, Hidetoshi Onodera:
Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365 - [c5]Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees. ICCD 2001: 110-117 - [c4]Masanori Hashimoto, Hidetoshi Onodeva:
Increase in delay uncertainty by performance optimization. ISCAS (5) 2001: 379-382 - 2000
- [c3]Masanori Hashimoto, Hidetoshi Onodera:
A performance optimization method by gate sizing using statistical static timing analysis. ISPD 2000: 111-116 - 1999
- [c2]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451 - 1998
- [c1]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226
Informal and Other Publications
- 2022
- [i3]Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann:
VirtualSync+: Timing Optimization with Virtual Synchronization. CoRR abs/2203.05516 (2022) - 2021
- [i2]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR abs/2111.12330 (2021) - 2019
- [i1]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo:
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. CoRR abs/1909.04697 (2019)
Coauthor Index
[j76] [j75] [j73] [j71] [j67] [j66] [j65] [j64] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j49] [j48] [j46] [j45] [j44] [j42] [j40] [j36] [j35] [j32] [j31] [j26] [j25] [j24] [j23] [j18] [c96] [c91] [c90] [c88] [c87] [c86] [c85] [c84] [c80] [c79] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c63] [c62] [c61] [c60] [c59] [c56] [c55] [c54] [c53] [c52] [c50] [c49] [c48] [c45] [c43] [c40] [c38] [c37] [c34] [c32] [c31] [c30] [c29] [c23]
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